Branch delay slot

In computer architecture , a branch delay instruction is a machine instruction that directly follows a conditional branch instruction and is always executed regardless of whether the branch was taken or not. The position of such a machine instruction in the pipeline is called the Branch Delay Slot . Branch delay slots are used to better utilize the pipeline . They can be found in various RISC architectures such as MIPS , PA-RISC , SPARC and SuperH as well as in DSP architectures such as µPD77230 and TMS320C3x / TMS320C4x .

functionality

Processors using a pipeline split the execution of an instruction into several stages. Several commands are executed in parallel, with exactly one command being processed in each stage.

In the case of branch instructions, a so-called hazard occurs: when the next instruction is loaded, the branch instruction has not yet been completely executed; therefore it is not clear which instruction should be loaded. Therefore you have to wait for a branch instruction. The Branch Delay Instruction is used to take advantage of this waiting time. It is always executed, regardless of the result of the branch instruction.