SGS-Thomson ST20
The ST20 is a by SGS-Thomson -developed 32-bit - microprocessor . It is primarily used in the Omega chipsets (STi55xx) for digital receivers , but is also used in other areas such as GPS receivers .
variants
The following variants are known:
- STi5500: 2 kB I-cache, 2 kB D-cache, 2 kB SRAM, up to 50 MHz
- STx5188: 4 kB I-cache, 4 kB D-cache, 2 kB SRAM, up to 200 MHz
- STi5300: with ST231 CPU, 32 kB I-cache, 32 kB D-cache, up to 333 MHz
- STi5512: up to 60 MHz
- STi5514: 8 kB I-cache, 8 kB D-cache, 8 kB SRAM, up to 180 MHz
- STi5517: corresponds to the STi5514 in the specified data
- STi5518: with ST20C2 + CPU, 2 KB I-Cache, 2 KB D-Cache, 4 KB SRAM, clock up to 81 MHz
- STM5105: 4 kB I-cache, 4 kB D-cache, 2 kB SRAM, up to 200 MHz
- ST20GP6: with ST20C2 CPU and 12-channel GPS engine, up to 50 MHz
Internals
The processor is optimized for integer arithmetic (up to 64 bits) and does not contain a floating point unit. In principle, the architecture is based on the Inmos transputer . Inmos was bought by STMicroelectronics in March 1989. The "transputer core" is practically not noticeable, however, since the transputer links have been completely dispensed with.
The ST20 is a classic Von Neumann architecture with six registers:
- Data pointer (workspace pointer) Wreg
- Instruction pointer Ireg
- Status register status
- Data registers Areg, Breg, Creg
The organization of the three data registers Areg, Breg and Creg is a specialty. These three registers form an internal stack on which all arithmetic operations are carried out.
The rather extensive CISC instruction set supports multitasking through special instructions for communication between individual processes in terms of hardware.
There are two timer registers with a word length of 32 bits each and a resolution of one microsecond.
Operating systems
The manufacturer supplies the STlite system (also known as OS20 Real Time OS ). It is used in all digital receivers equipped with the STi55xx chipsets .