NAND logic
Like NOR gates, NAND gates can be combined to form any other kind of logic gate.
NAND
This is a NAND gate:
| Desired Gate | NAND Construction |
|
|
|
Typical CMOS construction: CMOS
| Input A | Input B | Output |
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
NOT
This is made by joining the legs of a NAND gate. As a NAND gate is equivalent to an AND gate leading to NOT gate, this automatically sees to the "AND" part of the NAND gate, leaving only the NOT part.
| Desired Gate | NAND Construction |
| Input A | Output |
| 0 | 1 |
| 1 | 0 |
AND
This is made by combining a NAND gate with a NOT gate as shown below. This gives a NOT NAND, i.e. AND.
| Desired Gate | NAND Construction |
|
|
|
| Input A | Input B | Output |
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
OR
If the truth table for a NAND gate is examined, it can be seen that if any of the inputs are 0, then the output will be 1. However to be an OR gate, if any input is 1, the output must also be 1. Therefore, if the inputs are inverted, any high input will trigger a high output.
| Desired Gate | NAND Construction |
|
|
| Input A | Input B | Output |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
NOR
A NOR gate is simply an OR gate with an inverted output:
| Desired Gate | NAND Construction |
|
|
| Input A | Input B | Output |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
XOR
| Desired Gate | NAND Construction |
|
|
|
| Input A | Input B | Output |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
XNOR
An XNOR gate is simply an XOR gate with an inverted output:
| Desired Gate | NAND Construction |
|
|
|
| Input A | Input B | Output |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |