OVPsim: Difference between revisions
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==[[Open source]] models== |
==[[Open source]] models== |
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Within OVP there are several different model categories. These models are provided as both pre-compiled object code, and as source files. Currently there are processor models of ARM, MIPS32, and OpenRisc families. There are also models of many different types of system components including RAM, ROM, cache, and bridge. There are also peripheral models including DMA, UART, and FIFO. There are also models of several different pre-built platforms including software like ucLinux to run on them. |
Within OVP there are several different model categories. These models are provided as both pre-compiled object code, and as source files. Currently there are processor models of ARM, MIPS32, ARC600/ARC700, and OpenRisc families. There are also models of many different types of system components including RAM, ROM, cache, and bridge. There are also peripheral models including DMA, UART, and FIFO. There are also models of several different pre-built platforms including software like ucLinux to run on them. |
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One of the main uses of the OVP simulation infrastructure is the ability to create and simulate your own models - either from scratch, or by using one of the open source models as a starting point. The OVP APIs are tailored to different model types: processors, behavioral models of peripherals, and platforms. |
One of the main uses of the OVP simulation infrastructure is the ability to create and simulate your own models - either from scratch, or by using one of the open source models as a starting point. The OVP APIs are tailored to different model types: processors, behavioral models of peripherals, and platforms. |
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Revision as of 11:44, 20 February 2009
| Developer(s) | Imperas |
|---|---|
| Stable release | 20080815.0
/ August 15, 2008 |
| Operating system | Windows |
| Type | Emulator |
| License | Apache 2.0 |
| Website | http://www.OVPworld.org |
OVPsim is a multiprocessor platform emulator that uses dynamic binary translation technology to achieve high simulation speeds. It has public APIs allowing users to create their own processor, peripheral and platform models. Various models are available as source at OVPworld.org[1]. OVPsim is a key component of the Open Virtual Platforms initiative.
Licensing
OVPsim is written and maintained by Imperas and is free software. various processor, peripheral and platform models are available as source at OVPworld.org[2] under Apache 2.0 licensing.
Details
There are three main components of OVP: open source models, free OVPsim simulator, and modeling APIs. These components are designed to make it easy to assemble multi-core heterogeneous or homogeneous platforms with complex memory hierarchies, cache systems and layers of embedded software that can run at 100s of MIPS on standard desktop PCs. At OVPworld.org[3] are many examples of components, and complete platforms.
Open source models
Within OVP there are several different model categories. These models are provided as both pre-compiled object code, and as source files. Currently there are processor models of ARM, MIPS32, ARC600/ARC700, and OpenRisc families. There are also models of many different types of system components including RAM, ROM, cache, and bridge. There are also peripheral models including DMA, UART, and FIFO. There are also models of several different pre-built platforms including software like ucLinux to run on them. One of the main uses of the OVP simulation infrastructure is the ability to create and simulate your own models - either from scratch, or by using one of the open source models as a starting point. The OVP APIs are tailored to different model types: processors, behavioral models of peripherals, and platforms.
OVPsim simulator
The OVPsim is available free at OVPworld.org[4]. The simulator uses dynamic binary translation technology to achieve very high simulation speeds (more than a billion simulated instructions per second is possible in some cases on regular Windows machines).
OVPsim comes with a GDB RSP interface to allow simulated processors to be debugged with any standard debugger that supports this GDB RSP interface.
OVPsim can be encapsulated and called from within other simulation environments and comes as standard with wrappers for C, C++, and SystemC. It is also possible to encapsulate legacy models of processors and behavioral models so that they can be used by OVPsim.
Modeling APIs
OVP models are created using C/C++ APIs. There are three main APIs: ICM, VMI, BHM/PPM.
- ICM
For platforms there is the ICM API for controlling, connecting, and observing platforms. This API can be called from C, C++, or SystemC. The platform provides the basic structure of the design and creates, connects, and configures the components. The platform also specifies the address mapping, and software that is loaded on the processors. It is very easy with ICM to specify very complex and complete platforms of many different processors, local and shared memories, caches, bus bridges, peripherals and all their complex address maps, interrupts and operating systems and application software.
- VMI
For processor modeling there is the VMI API. These API functions provide the ability to easily describe the behavior of the processor. A processor model written in C using the VMI decodes the target instruction to be simulated and translates this to native x86 instructions that are then executed on the PC. VMI can be used for modeling 8, 16, 32, and 64 bit architectures. There is an interception mechanism enabling emulation of calls to functions in the application runtime libraries (such as write, fstat etc) without requiring modification of either the processor model or the simulated application.
- PPM & BHM
Behavioral components, peripherals, and the overall environment is modeled using C code and calls to these two APIs. Underlying these APIs is an event based scheduling mechanism to enable modeling of time, events, and concurrency. Peripheral models provide callbacks that are called when the application software running on processors modeled in the platform access memory locations where the peripheral is enabled.