Cache consistency
Cache consistency is the state in which all copies of a memory word in the caches and in the main memory are identical. If a cache contains newly written data that has not yet been written to main memory, it is temporarily inconsistent . In write-back caches, this is marked with a so-called dirty or modified bit. However, inconsistency can also arise from write accesses by other components to the shared main memory. This can be additional caches such as multiprocessor systems with split cache or other writing components such as peripheral devices with DMA .
Distinction between consistency and coherence
Cache consistency ( Latin con 'together' and sistere 'hold') describes a state. Cache coherence (Latin cohaerere , to be related) describes a property of several caches working on a common main memory. The entire system of caches and main memory is referred to as cache-coherent if the last value written is always returned with each read access. It shouldn't make any difference which cache was last written to. A cache-coherent system can be temporarily inconsistent.
This temporary inconsistency is even necessary, since constant consistency would mean that the entire system has to orient itself to the slowest component (usually the main memory) when writing ( write-through ). In order to be able to establish coherence without constant consistency, cache coherence protocols such as MESI are used. To put it casually, a cache coherence protocol manages precisely this inconsistency within all components that access the main memory.
Cache consistency describes the uniform status of several memories involved, while cache coherence describes the uniform view of the data for the processing components (mostly CPUs).
See also
Individual evidence
- ^ John Hennessy, David Patterson: Computer Architecture. A Quantitative Approach., 4th Edition, Morgan Kaufmann Publishers, ISBN 978-0-12-370490-0 (English)