Pipeline hazard

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Pipeline hazards are conflicts in the pipeline of processors that can occur during program runtime.

All modern processors are designed in a pipeline architecture: the individual instructions run through a multi-stage pipeline in which they reach the next stage with each clock cycle. Part of the processing of the instruction is carried out in each stage. Each sub-step requires certain processor resources (e.g. data paths and arithmetic units) and possibly the results of a previous instruction. If one of these resources is blocked by another instruction or results are not yet available, this instruction and all those following in the pipeline must be temporarily “stalled”.

There are three types of pipeline conflict:

Data conflicts

Data conflicts arise from data dependencies between commands in the program. There are three types of data conflicts.

1. Read after Write (RAW) or real dependency : An operand was changed and read shortly afterwards. Since the first instruction may not have finished writing the operand (pipeline stage “store” is far behind), the second instruction would use incorrect data. A “shortcut” in the data path of the pipeline can avoid the hazard. In more problematic situations, for example if a calculation result is used for addressing or in the case of calculated and conditional jumps, the pipeline must be stopped.

example

   R1 = R2+R3
   R4 = R1+1

2. Write after Read (WAR) or counter-dependency : An operand is read and overwritten shortly thereafter. Since writing could already be completed before reading, the read command could receive the newly written values. Not a problem in the normal pipeline.

example

   R1 = R2+R3
   R2 = 2

3. Write after Write (WAW) or output dependency : Two commands write to the same operand. The second could be terminated before the first instruction, leaving the operand with an incorrect value.

example

   R1 = R2+R3
   R1 = 2

Tax disputes

Control conflicts occur with instructions that change the command counter, e.g. B. with conditional jump commands.

These types of conflicts can be avoided by doing the following:

• Jump prediction : An additional hardware unit calculates the probability that a jump will occur.
• Delayed branching : During the time in which the jump destination is being calculated, the CPU can be used to calculate other instructions that are independent of the jump. Delayed branching is out of date; it is being replaced by dynamic branch prediction algorithms.

Structural conflicts

Structure conflicts occur when there are resource conflicts within instructions in the pipeline, e.g. B. a synchronous access to a register memory with only one input.

In this simple case, all processors can avoid the hazard with a “shortcut” in the data path of the pipeline, but in more problematic situations, for example when a calculation result is used for addressing or for calculated and conditional jumps, the pipeline must be stopped.

The example shows that it makes sense not to execute interdependent commands in direct succession. Modern processors can therefore in many cases avoid hazards and resource conflicts through out-of-order execution or hardware-based multithreading .