Storage sharing

from Wikipedia, the free encyclopedia
Basic scheme

In a memory interleave (from the English memory interleaving ) is the memory in the same size, independent areas ( modules , memory banks) is divided, can be read in time interleaved or described. Successive memory words are stored cyclically in successive memory banks.

If the memory has a lower clock rate than the processor, the alternating access reduces the waiting times for memory operations. A slower memory module has more time to process a single access, the memory looks faster to the processor. In practice, this has considerable effects, since modern processors are usually faster than main memory, which is why other methods, above all several levels of cache memory, are attempting to increase the main memory to the speed level of the processors.

Individual evidence

  1. from Thomas Dorn: Numerical Mathematics, interactive