Command decoder
The command decoder is part of the processor in the computer, a so-called interpreter .
Its task is to translate the machine commands into micro instructions and, if necessary, to break them down into individual work steps. These are then forwarded by him to the associated units of the central processing unit .
In a typical microprocessor with a pipeline, the instructions are fetched from memory by the instruction fetch unit (IFU) and then passed to the instruction decoder. The stored value can then be used to decode the next command. Humanly speaking, this corresponds to looking up a table. In addition to decoding the command (e.g. addition or jump), the operands must also be decoded. In the case of addition, for example which values should be added.
How difficult this process is depends on the architecture of the processor. In the best case, it is a RISC (Reduced Instruction Set Computer) processor, in which every instruction is stored with the same number of bits. Also, when the instruction is decoded, it is not necessary to generate new micro-instructions if the stored instruction requires, for example, an operand to be loaded from the memory. This can happen with CISC (Complex Instruction Set Computer) architectures. A further complication with this architecture is that the commands are often of different lengths, i.e. they need different numbers of bits for storage. The most famous representatives of this problem are the processors compatible with the x86 instruction set.
It is similarly simple with processors with VLIW (Very Long Instruction Word) architecture. Instructions of this architecture are relatively easy to decode, but besides the desired operation and the operands also contain information about the execution units to be used.
The decoded instructions are forwarded to the subsequent execution units. The next command can then be decoded.