Von Neumann cycle

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In technical computer science, the Von Neumann cycle describes a process in the processing of commands in a classic Von Neumann computer .

Today, however, modern microprocessors use separate caches for data and instructions and can therefore be referred to as modified Harvard processors or as Fast-Von-Neumann processors, which is why they have little in common internally with the classic Von-Neumann cycle.

The sub-steps

Von Neumann cycle

The cycle consists of five sub-steps

  1. FETCH - command call : The next command to be processed is loaded from the memory into the command register according to the address in the command counter and the command counter is increased by the length of the command.
  2. DECODE - decoding : The command is resolved by the control unit into switching instructions for the arithmetic unit.
  3. FETCH OPERANDS - operand fetch : The operands are now fetched from the memory. These are the values ​​that are to be changed by the command or that are used as parameters.
  4. EXECUTE - command execution : An arithmetic or logical operation is carried out by the arithmetic unit. In the case of jump commands and fulfilled jump conditions, the command counter is changed at this point.
  5. WRITE BACK - Writing back the result : If necessary, the result of the calculation is written back to the memory.

The last three phases of the Von Neumann cycle do not have to be executed for every type of command. Many arithmetic and logic commands of the current CPUs actually do not write their result back to the main memory (HS). This is done later by a separate storage command in which only the WriteBack phase is of interest and therefore the operand call is missing and the Execute phase is "stunted". On the other hand, with multi-address machines, the result is usually written to the HS immediately. But all modern processors also have commands that immediately write their result back to the HS, for example the increment command related to a storage location or the Exchange command. This is neither rare nor does it require special hardware. In order to save an additional address specification in the command, the result is "written back" to the same location of an operand (write back).

A partial step can take several cycles . After the cycle has ended, it starts again from the beginning and another command is processed. It should be noted that the last three phases of the cycle do not all have to be executed for every type of instruction . For example, many arithmetic and logic commands of the current CPUs do not immediately write their result back to main memory . This is done later by a separate save command in which only the WriteBack phase is run through.

Modern central processors have clock frequencies of 2 to 5 GHz. With current processors

  • several of these sub-steps mentioned above are carried out in parallel (simultaneously) by so-called pipelining ,
  • each sub-step is generally carried out several times per cycle. When executing commands, this is called ports. For example, the Haswell CPU can restart up to 8 new commands per cycle, the execution time of which is usually between 1 and 5 cycles, so that up to 40 machine instructions can be in the EXECUTE phase.

Additional performance-enhancing features are:

  • SIMD commands
  • Multiple cores

This means that current processors in mainstream PCs can execute up to 2000 arithmetic commands in parallel. These values ​​are practically unattainable.


The next command to be processed is loaded into the command register, which together with the control and arithmetic logic unit (arithmetic-logic unit, ALU) represents the main processor (CPU) from RAM or ROM memory. Then the instruction counter (the instruction pointer ) is incremented so that it points to the next memory location. This increase is already necessary here so that a jump command with "return intent" (subprogram jump) can save the address of the following command before the jump.

Processors can often load several instructions from memory into a buffer (prefetch register block) while the current instruction is still being executed. This process is known as OpCode Prefetching (German operation code prefetching ).

  1. Advantage: Significant increase in processing speed because the effect of the Von Neumann bottle neck is reduced.
  2. Disadvantage: In the case of program branches, the "unnecessarily" loaded commands may have to be discarded.

Web links

  • μRISCy - RISC simulation calculator for advanced exercises
  • MOPS is a model computer that clearly shows the Von Neumann cycle
  • JOHNNY is an open source simulator that clearly shows the Von Neumann cycle.