Harvard architecture

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Schematic representation of the Harvard architecture. Data and commands are in separate memories and, in this example, can be loaded into the arithmetic units in parallel.

In computer science, the Harvard architecture describes a circuit concept in which the instruction memory is logically and physically separated from the data memory. The logical separation results from different address spaces and different machine commands for access to command and data memory. The physical separation is implemented with two separate memories, each of which is accessed via its own bus. A less strict separation of instruction and data memories is called a modified Harvard architecture.


The advantage of this architecture is that commands and data can be loaded or written at the same time. With a classic Von Neumann architecture , at least two consecutive bus cycles are necessary for this.

In addition, the physical separation of data and program ensures that a separation of access rights and memory protection can be easily implemented. To z. For example, to prevent program code from being overwritten in the event of software errors, a memory that can only be read during operation (e.g. ROM , punched cards ) is used for the program code, and writable and readable memories (e.g. RAM , toroidal core memory ) for the data ).


The name "Harvard architecture" has its origins in the electromechanical computer Mark I , which was developed in cooperation between IBM and Harvard University and put into operation in 1944.

The Harvard architecture was initially implemented consistently mainly in RISC processors. Modern processors in Harvard architecture are able to fill several arithmetic units with data and commands at the same time. With signal processors of the C6x family from Texas Instruments, this is possible, for example, for up to eight arithmetic units.

Another advantage of the separation is that the data word width (the smallest addressable unit) and the command word width can be defined independently of one another. This can, if necessary, also improve the efficiency of the program memory requirement, since it does not depend directly on the data bus widths, but exclusively on the instruction set. This can e.g. B. in embedded systems or small microcontroller systems of interest.

Single-chip microcontrollers that work with fixed programs mostly use the Harvard architecture. Well-known representatives are z. B. ( PICmicro ) from Microchip Technology , the Intel 8048 and 8051 families , the STM8 from STMicroelectronics and the AVR series from Microchip Technology.

A significant expansion of the Harvard architecture was made by the American company Analog Devices in the early 1990s with the introduction of the Super Harvard architecture technology, in which the memory segments mentioned are designed as dual-port RAMs that cross between the programs - and data buses lie.

Many modern processors use a hybrid of Harvard and Von Neumann architecture, in which data and program are managed separately within the processor chip, have their own caches and MMUs and run on separate internal buses, but are externally in a common memory. If CPU pipelining is implemented, the advantage of this hybrid form (at the processor level) is that its individual pipeline stages can be separated with regard to memory accesses. A typical example of this type of processor is the Motorola 68030 , which was developed in the 1980s.

See also