Super Harvard architecture
Super Harvard architecture is the term coined by Analog Devices for a modification of the Harvard architecture in digital signal processors . The extension consists in the fact that instructions are temporarily stored in a cache and the instruction bus is used for the transfer of operands. In addition, the processor is relieved of this task through direct data transfer between the command and data memory.
architecture
The Super Harvard architecture is optimized for higher data throughput and differs in essential points from the classic Harvard architecture.
Many operations require two operands. This requires three bus accesses, since both the command and the two operands are required. In order to reduce the number of bus accesses and to be able to use two buses for data transmission, a cache is used for commands and the command memory is also used for data.
Initially, the problem of successive accesses is only shifted from the data bus to the command bus, but the buffering of the command means that both buses remain free for the operands during repeated execution. The advantage of the bus access saved increases with each iteration.
The problem of transferring the data into this memory arises from the use of the instruction memory for data. According to the Harvard architecture, the two memories would only be connected to one another via the processor. However, data transfer involving the processor would destroy the optimization by the instruction cache. For this reason, data is transferred between the two memories using DMA .
Processors
Analog Devices
Analog Devices' SHARC processors have been 32-bit floating point DSPs available since 1993 . Analog Devices' registered trademark SHARC is a contraction of the architecture name.
In addition to the two fundamental changes, this processor also has a double set of registers and address generators, so that you can switch between the registers. This enables a quick change between two tasks without first having to write the command and data back to the memory and fetch the new command and the data. It also has six link ports through which other processors of the same type can transmit and receive data. Together with the built-in timer, it is suitable for parallel processing of data by several processors.
The SHARC processors were originally aimed at compute-intensive applications that required multi-processor systems. Today, however, this field is mainly covered by the so-called TigerSHARC processors from the same company.
Texas Instruments
The Texas Instruments TMS320C processor family also has a Super Harvard architecture.
Web links
Individual evidence
- ^ A b Steven W. Smith: Chapter 28: Digital Signal Processors - Architecture of the Digital Signal Processor. In: The Scientist and Engineer's Guide to Digital Signal Processing. Retrieved May 2, 2010 (English).
- ↑ SHARC Processor Architectural Overview - Super Harvard Architecture. Analog Devices , accessed May 7, 2010 .
- ↑ a b c DSP processors: memory architectures. In: Introduction to DSP. Bores Signal Processing, accessed May 7, 2010 .
- ↑ Simon Parry: Analog Devices releases Sharc into DSP waters. In: Electronics Weekly. October 13, 1993, accessed May 7, 2010 .
- ↑ TMS320C40 digital signal processor. (PDF) Texas Instruments, January 1996, accessed May 7, 2010 (processor data sheet).