Direct storage access

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The term direct memory access or English Direct Memory Access ( DMA ) referred to in the computer technology , a type of access, via a bus system accesses the memory.

This technology allows connected peripheral devices , such as. B. network card or sound card to communicate directly with the memory without detour via the CPU . The advantage of direct memory access is the faster data transfer while at the same time relieving the processor.

Direct memory access is also possible via network connections using remote direct memory access , provided the hardware and operating system support this.

Direct memory access

Input / output via processor
Input / output via direct memory access

The conventional method of transferring data from an input / output unit to the main memory uses processor registers for intermediate storage. First, the processor reads the data into its internal register, and then moves it to the main memory in a further step. This requires many clock steps in which the processor is not available for the execution of other instructions, and thus the execution speed of running programs is reduced.

Direct memory access is a circuit and control measure that creates a connection between plug-in cards (or I / O on the motherboard itself) and the main memory via special data lines on the motherboard. This means that the data can be written directly to the memory without going through the processor, and the execution speed of running programs is not affected.

The PC only has one real DMA line. Access to the various components (plug-in cards) is differentiated using an index. Accordingly, a DMA index can only be assigned to one device. The index indicates the number of the DMA channel. There are a total of 8 DMA channels. Channels 0, 2 and 4 are already permanently assigned for internal purposes. Channels 1, 3, 5, 6 and 7 can be freely assigned. Channels 0–3 work with 8, channels 4–7 with 16 bits.

How the DMA controller works

The DMA controller (DMA-C) is integrated in modern chipsets . Older motherboards have a separate component such as the 8237 or the 8257 from Intel.

If the I / O hardware wants to send or receive data, the DMA controller disconnects the processor from the bus system . The DMA controller then executes the request at high speed. The connection between the processor and the bus system is then restored. The processor needs up to 40 cycles per byte for the memory transfer. The DMA controller performs the access within four cycles.

The DMA controller is used to transport data between the main memory and peripherals. This relieves the processor. In addition to an increase in speed for memory-intensive applications, the use of DMA controllers also enables very high data rates, e.g. B. When burning DVD media. Even with current PC systems, burning speeds of 16 × are not possible without DMA support.


The DMA controller must inevitably transmit the data via the same data, address and control lines of the respective bus system as the CPU otherwise. It must therefore be ensured that the CPU and DMA controller do not collide. For this purpose, an " arbitration " is carried out in advance , a procedure in which the DMA controller requests control of the buses from the CPU, the latter grants this at the next opportunity and then releases the buses. After the DMA transfer is complete, the bus request is withdrawn and the CPU can take over again.

There are various electronic implementations for this, with different numbers of control lines. The simplest variant has a bus request line (request) from the DMA controller to the CPU and a bus grant line (granting) in the opposite direction.

Addressing method

There are two different addressing methods. With so-called Explicit Addressing (also Two Cycle Transfer ), the DMA controller first fetches a data word (or byte) and saves it in an internal register (like a CPU). Then it addresses the target component and transfers the data to it. Two bus cycles are therefore required for this procedure. - With implicit addressing (or single bus transfer ), there is no intermediate storage in a register: The DMA controller addresses the data word to be fetched and immediately puts it through to the target module. Only a single bus cycle is required. This method is not suitable for memory-to-memory transfers, since only one address can be present in the memory at a time.

However, the DMA method is only efficient if not only a single data word is to be transmitted, but rather larger contiguous memory areas, e.g. B. entire data sectors or tracks from a hard drive . Then the certain overhead is worthwhile, which arises from the fact that first of all the DMA controller has to be set up for the upcoming task by setting various register contents.


The classic DMA technology of the ISA bus is based on signaling the peripherals for transfer requirements through individual data lines, the so-called DMA channels. If such a channel is now activated, circuits belonging to the bus control supply addresses to the bus that can be incremented or kept constant per cycle, while the initiating peripheral circuit either receives the connected data or itself receives data on the Bus connects. Since direct memory access interrupts normal bus activity, operation with the CPU is not possible during this period. Since there are several DMA initiators, appropriate priority schemes must be used. Furthermore, a DMA channel must first be initialized and the connection of the bus with address and control signals must also first be specified by software. After a successful transfer, an interrupt is usually triggered that informs the system software that the process is complete. The DMA circuits are then usually reprogrammed so that they point to the next data block to be processed.

Development directions for DMA controllers

In the broader sense, a DMA controller must be understood to mean any module that can access memory (either to the main memory itself or to a peripheral component) without using the CPU. This basic principle can, however, be varied in many ways. There are systems with a central DMA coprocessor, for example, but also systems in which each component has its own decentralized DMA controller. The latter method differs from the use of a central controller in that there are no DMA channels. Rather, the requesting circuit reserves the bus for itself and addresses it itself. Each component, such as processor or peripheral components, can be the initiator that takes over the command over the main memory (addressing, data transfer and bus control signals). The bus master now transmits the data intended for it to its destination, the target . In principle, only one component can be the bus master at any one time. For example, PCI controllers can also be DMA bus masters at the same time.

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Individual evidence

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