Reduced Instruction Set Computer

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Reduced Instruction Set Computer ( RISC , English for computers with reduced instruction set ) is a design philosophy for computer processors . The term was coined in 1980 by David A. Patterson and Carlo H. Séquin . The design goal was to dispense with a complex instruction set , which is comfortable for assembler programming , towards instructions that are easy to decode and can be executed quickly (“actual instruction execution” usually only 1 cycle). This also made higher clock frequencies possible .

The design philosophy opposite to RISC is called Complex Instruction Set Computer (CISC). Today the distinction between RISC and CISC has largely lost its importance. Former RISC processor families have meanwhile also included more complex instructions; CISC processors have received RISC-like design components since the mid-1990s and are also superscalar . The decoding of commands takes up only a small part of the chip area regardless of RISC or CISC. The main area of ​​the chips is now taken by processing units that have only appeared in processors since the early 1990s.

RISC design philosophy

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Instruction sets from processors of the 1980s became increasingly larger. New orders were added, old orders that were hardly needed were retained. Very complex commands and addressing types emerged, which were difficult to use by compilers and even by assembler programmers. Using the KISS principle , the RISC processor of the 1980s / 90s was to receive a simple instruction set that was quick to decode and easy to execute. A RISC instruction set dispenses with complex instructions - especially those that combine memory accesses (slow) with arithmetic operations (fast). As a result, the stages of the processor pipeline can be coordinated well, the stages become shorter, the pipeline can be clocked faster and it is better utilized because fewer “ stalls ” occur. In addition, simpler instructions can be coded more consistently than with CISC architectures, which further reduces the decoding effort and thus the pipeline latency. The instruction set of CISC processors is mostly implemented in the form of microcode . With RISC processors, however, the individual commands are hard-wired. This enables the instruction set to be implemented with relatively few transistors ; the commands are partially processed in parallel and very quickly.

Consideration of new knowledge at the time when building the compiler:

The background to the development of RISC architectures was:

  • The extensive change from assembly language programming to high-level language programming in the 1980s. Even operating systems were increasingly written in higher languages.
  • Sufficient main memory to be able to carry out complex optimizations in compilers in the first place.
    Enough main memory for the somewhat longer code (which RISC brought with it at the time).
  • They wanted to get a lot of computing power out of the 0.2 to 2 million transistors of a CPU that were possible at the time.

The following properties are typical for RISC processors:

  • All commands follow the same or very few flowcharts (fetch, decode, ...)
  • Properties largely resulting from this:
    • The commands have a constant length (mostly 32 bits).
    • Little variation in execution time, often constant. In early designs, the actual execution time was often 1 bar. Later designs tend to use 1 cycle per pipeline stage, but still achieve a throughput of 1 instruction per cycle thanks to superscalarity .
      Commands that could not be implemented in this way (integer division) were mostly left out and replaced by several simpler commands that did this job together.
    • Decoupling of memory read operations and arithmetic (“ load / store architecture ”).
  • Superscalar architecture, pipelining with at least 4 stages (also at CISC since the 1990s).
  • The development of the CPU and the ( C ) compiler run in parallel and have a massive influence on each other.
  • RISC architectures lead to more temporary intermediate results, which is why they have at least 16 general purpose registers (meanwhile also with CISC).
  • Often Harvard or Super Harvard architectures.

The following things are only found with RISC processors, but are primarily the result of performance optimization or the saving of chip area:

  • Delayed Branches: The 1 to 3 following commands after jump commands are also executed.
  • Many processors do not perform locking of processor pipeline by increments, this design was the MIPS architecture , even the name ( M icroprocessor without i nterlocked p ipeline s day).


Typical properties of RISC processors

Although there is no formal definition of the term RISC, the majority of RISC processors have the following characteristics:

Super scalarity

The "actual command execution" usually only takes 1 clock cycle per command.

One command is started per cycle and a (previous) command is ended in each cycle. The decoding takes place without microcode through a hardwired network. A classic RISC processor executes commands in four cycles: Fetch, Decode, Load, Execute. There is always one command in each of these levels.

Load store architecture

In a load store architecture , only load and store commands access the main memory . All other instructions work exclusively with register operands and literals . These load and store commands do not have any complex address modes ; instead, the addresses are calculated in freely usable registers . However, only a few RISC CPUs have a classic load store architecture; most of them allow a memory operand.

Large number of freely usable registers and three-address code

To enable the compiler to efficiently generate code and optimize programs, RISC processors have a large number of freely usable registers (typically 16 or 32) and instructions in three-address code . Instructions in the three-address code have one destination and two source registers. The Berkeley RISC processor and its descendants (including Sun SPARC , AMD Am29000 and Intel i960 ) also have register windows that allow a particularly large number of registers and accelerate the call of subroutines .

Commands with fixed length and few formats

All commands are of the same length and there are only a few command formats . This means that the position of the opcode , register operands and literals is the same for almost all commands , which considerably simplifies and speeds up decoding. 32-bit wide command words and five different command formats are typical. Notable exceptions are IBM's original 801 , ARM's Thumb , microMIPS, and Infineon TriCore . These RISC architectures use variable instruction lengths of 16 and 32 bits in order to shorten the program code.

history

Beginnings

The beginnings of RISC go back to the 1960s. In the late 1970s and early 1980s, several factors finally came together that led to a new design philosophy and a wave of new processor designs:

  • The introduction of the memory hierarchy of fast caches and cheap main memory made the speed advantages of microprogram memories obsolete.
  • The compilers became more complex and generated faster code, for example by removing the register assignment by coloring the graph , removing common partial expressions, using faster equivalent instructions, by statically evaluating expressions at compile time and by removing dead program code. Many of these optimizations can not reach their full potential on microprogrammed processors because they cannot be applied directly to the internal microcode .
  • Advances in semiconductor integration made it possible to integrate fast, more complex processors made up of more and more transistors on one chip . Together with the new VLSI CAD tools, the integration led to a significantly higher productivity, so that new developments were possible with relatively few staff. The shorter development cycles allowed a rapid evolution of the design philosophy.
  • The ARPA , the research agency of the US Department of Defense, supported at this time targeted projects for the development of integrated circuits , including the RISC project in Berkeley, the MIPS project at Stanford and many other follow-up projects.

Important pioneers for RISC were the CDC 6600 ( Seymour Cray and Jim Thornton , 1964) and IBM's ACS project ( Jack Bertram and John Cocke , from 1963). Some early RISC projects and architects:

Heyday

When, after initial doubts, the benefits of RISC became apparent, practically all computer manufacturers began to develop their own RISC architectures:

As a result, the term RISC had a positive connotation and was used inflationarily in advertising (e.g. by Intel for the 486 ). By Steven A. Przybylski following ironic definition of RISC is handed down, "a computer that was announced after 1985".

Compared to CISC

The list of the SPEC ( Standard Performance Evaluation Corporation ) with the fastest processors is now very heterogeneous. You can find “RISC processors” such as “CISC processors” as well as processors that are derived from graphics processors. The scalability of the architecture for the parallel operation of tens of thousands to hundreds of thousands of cores is important for supercomputers. In the meantime, the majority of the processors in the TOP500 are x64-compatible "CISC processors" (76 percent: Intel Xeon and AMD Opteron). As a “RISC processor”, the IBM Blue Gene (PPC) is right at the front with 18 percent.

In current mainframes, however, pure / extensive RISC chips have now been almost completely replaced by the microprocessors of the Intel x86 line, which combine a RISC core with a CISC emulation layer. Their origins in the successful mass market use make the small series of the mainframe RISC chips unprofitable. DEC Alpha has been discontinued, as have HP's PA-RISC, Sun's SPARCs are no longer produced, PowerPC chips are only manufactured by IBM itself, Renesa's SuperH is hardly more widespread, XScale, MIPS and StrongARM are rare or have disappeared in mainframes. (Status 2011)

RISC processors are the counterpart to CISC processors. Today's RISC processors exceed the limits of the narrow definition and also contain more complex instructions. The instruction set of the PowerPC processor, which is manufactured by IBM and Freescale (formerly Motorola ) (and was used in Apple computers until the switch to Intel CPUs ), was supplemented by an instruction extension called " AltiVec ", which retrofitted special multimedia capabilities in the PowerPC processors (compare MMX for x86 processors ). However, AltiVec also follows the RISC properties.

The end of the 1980s, the British manufacturer brought Acorn the home computer Archimedes with a specially-designed RISC processor on the market, its performance placed the time of the processors used in home computers in the shade. This A corn R isc M achine was the origin of the current ARM processors built on the embedded systems are very common (for example, mobile phones).

Practical meaning - systems with RISC CPU

  • ARM - The ARM architecture is probably the most successful RISC family in terms of number of units. It can be found in many systems that require relatively high performance, low power consumption and low costs (typically: 100–500 MHz, sometimes up to 2 , 7 GHz; as of 2015). ARM Ltd., which constructs these systems, does not build any processors itself, but only sells licenses for the design to its customers. Meanwhile, 10 billion ARM CPUs are said to be in circulation. B. are used in tablets , digital cameras , graphical pocket calculators , NAS , routers , game consoles , PDAs , smartphones and various mobile phones. A use for energy-saving servers is aimed for in the near to medium future, which is why ARM presented the first processors with 64-bit architecture in 2012 .
  • Power Architecture - A development by IBM and Freescale (formerly Motorola ), is the most widespread RISC CPU in the high-end area today, it is an architecture with numerous areas of application, starting with powerful embedded systems such as printers or routers , via workstations , to supercomputers.
  • MIPS - At the beginning the CPUs were mainly used in classic workstations and servers, today the main area of ​​application, similar to ARM, is in the area of embedded systems . Virtually all MIPS-based workstation and server families have now been migrated to Intel Itanium .
  • Oracle's (formerly Sun Microsystems ) SPARC product line was primarily used in classic Sun workstations and servers.
  • Hewlett-Packards PA-RISC - Until the introduction of the Intel Itanium, PA-RISC CPUs were mainly used in classic workstations and servers from HP. The CPU family is no longer being developed. Virtually all PA-RISC-based workstation and server families have now been migrated to Intel Itanium.
  • DEC Alpha - Until the introduction of the Intel Itanium CPUs, Alpha CPUs were mainly used in classic workstations and servers from Digital, Compaq and HP. The Alpha platform was freely available and used by numerous OEM partners. The CPU family is no longer being developed. Virtually all Alpha-based workstation and server families have now been migrated to Intel Itanium.
  • Hitachi's SuperH , was widely used e.g. B. in the game consoles Sega Super 32X , Sega Saturn and Dreamcast . Today, like the ARM platform, SuperH is mainly used in embedded systems .
  • Atmel AVR is used in embedded systems such as: B. Xbox control controllers, but also in BMW automobiles.
  • The OpenRISC project takes up the philosophy of free hardware . The aim of the project is to create a CPU that runs Linux and that - in the sense of free software - is freely available.
  • RISC-V is another free instruction set based on the RISC principles.

Web links

References and comments

  1. ↑ David A. Patterson, Carlo H. Séquin: RISC I: A Reduced Instruction Set VLSI Computer. (English)
  2. ↑ George Radin: The 801 Minicomputer, 1976. (English)
  3. ↑ David A. Patterson, David R. Ditzel: The Case for the Reduced Instruction Set Computer, 1980. (English)
  4. ↑ David A. Patterson: Reduced Instruction Set Computers, 1985. (English)
  5. ↑ John Cocke, Victoria Markstein: The Evolution of RISC Technology at IBM, 1990. (English)
  6. ↑ Mitch Alsup: Motorola's 88000 Family Architecture, 1990. (English)
  7. ↑ ARM examples:
  8. ↑ AnandTech: The Motorola Nexus 6
  9. ↑ Heise Online: ARM is attacking 64-bit servers
  10. ↑ ARM press release: ARM Launches Cortex-A50 Series, the World's Most Energy-Efficient 64-bit Processors
  11. ↑ PowerPC examples:
    • Apple: PowerPC-based Macintosh computers
    • Cisco : Routers and switches for commercial use up to enterprise class
    • IBM: supercomputers, mid-range servers and workstations
    • Nintendo: Gamecube and Wii game consoles
    • Microsoft : Xbox 360 game console
    • Motorola: various on-board computers for cars and other vehicles
  12. ↑ MIPS examples:
  13. ↑ SPARC examples:
    • K computer Japanese supercomputer
    • Fujitsu supercomputers, mid-range servers and workstations
    • Sun: supercomputers, mid-range servers and workstations
  14. ↑ PA-RISC examples:
    • Hewlett-Packard: Supercomputers, mid-range servers and workstations, but also graphics cards
    • Hitachi: workstations
    • Stratus: Stratus Continuum series, highly available supercomputers
  15. ↑ OpenCore - OpenRISC - Article at PPCNUX , June 28, 2011
Processor architectures
according to word length

1-bit architecture  • Bit-slice architecture  • 4-bit architecture  • 8-bit architecture  • 16-bit architecture  • 32-bit architecture  • 64-bit architecture

according to instruction set structure

CISC  • EPIC  • NISC  • RISC  • VLIW  • Microarchitecture

with optimization for purpose

(Main) processor  • Graphics processor  • GPGPU  • Stream processor  • Sound processor  • Floating point unit  • Network processor  • Physics accelerator  • Vector processor  • TensorFlow Processing Unit