NISC

No Instruction Set Computing ( NISC ) is a computer architecture and compiler technology for developing highly efficient custom processors and hardware accelerators, where a compiler allows one to have very low-level control over the hardware.

Overview

NISC is a static-planned horizontal nano-coding architecture (SSHNA). The term “statically planned” means that the process execution and error control are in the hands of the compiler.

The term "horizontally nano-coded" means that NISC does not use a predefined instruction set or microcode . The compiler generates nanocodes for direct control of the instruction set or microcode.

The compiler generates nanocodes for direct adaptation of the arithmetic units , the registers , the multiplexers and the bus systems .

It gives the compiler control at a lower level for better utilization of bus system resources, which ultimately leads to higher performance.

The advantages of the NISC technology are:

• Simple controller: No hardware scheduler, no instruction decoder
• Better performance: More flexible architectures, better resource utilization
• Easier design: no need to design instruction sets

At its core, NISC is based on the concept of using intelligent compilers to get powerful FPGAs to generate programs that e.g. B. were written in high-level languages ​​such as C to translate in real time into FPGA-understandable hardware description languages similar to VHDL or Verilog .

EDA developers have devised methods with which FPGA systems can be implemented without VHDL and which already convert a standard ANSI-C source code directly into a digital circuit equivalent. Such compilers have been developed by both the FPGA manufacturer Altera (C2H compiler) and the EDA specialist Altium (CHC compiler). This also gives programmers access to FPGAs who previously had no knowledge or experience with VHDL and Verilog.

Provided that a standard is developed that regularly brings all program fragments into FPGA-compatible form, this could open the way for FPGAs to home PCs instead of the hard-wired processors that are still common today.

Individual evidence

1. ↑ Paul Goossens: FPGA “made easy” Program FPGAs in C! In: elektor . No. 3 , 2008, p. 36–41 ( PDF [accessed January 8, 2013]). PDF ( Memento of the original from September 3, 2013 in the Internet Archive ) Info: The archive link was automatically inserted and not yet checked. Please check the original and archive link according to the instructions and then remove this notice.