Complex Instruction Set Computer

CISC is a redirect to this article. Further meanings are listed under CISC (disambiguation) .

Complex Instruction Set Computer ( CISC ; English for computers with complex instruction sets ) is a design philosophy for computer processors . The name is a retro name that was coined with the introduction of the RISC processors. The Intel x86 processor family (up to and including 80386) is one of the best-known representatives of this concept.

development

Initially, the instruction sets of the processors became more and more extensive in order to be able to carry out more complex computing steps "at once" with only one machine instruction , in order to become faster and more efficient. At the same time, however, the processor also became complex and difficult to develop further - and also more difficult to program. Many manufacturers initially relied on the micro-programming of the arithmetic units in order to be able to correct problem cases more easily - but the complexity continued to increase.

The designation CISC was chosen by IBM in the 1970s to differentiate classic instruction sets from a new type, the Reduced Instruction Set Computer ( RISC ). A CISC instruction set is characterized by a large number of relatively powerful individual instructions, whereas RISC largely dispenses with complex instructions in favor of a high execution speed and lower decoding effort.

CPUs with the CISC instruction set were microprogrammed for a long time . Today you can hardly find any micro-programmed CISC CPUs. Starting with the Pentium Pro , the Intel processors have an upstream functional unit that translates complex commands into RISC-like simple commands, which a RISC-like CPU core then executes. Depending on the manufacturer and CPU, these units are called ROP, Micro-Op or µOp .

Examples of CPUs with the CISC instruction set are the Intel 8086 , the Intel 80386 , the Motorola 68000 , the Zilog Z80 and the CPUs of the System z series from IBM.

Web links

• Comments on CISC and RISC
• Risc vs. Cisc using the example of Intel