Intel Pentium Pro
The Pentium Pro is a microprocessor from Intel . It comes from the x86 / IA-32 architecture and is optimized for 32-bit program code. Since it was expensive and did not perform well with the 16- bit programs and operating systems (e.g. Windows 3.1x ) that were widespread at the time , it sold significantly worse than Intel had hoped. It was mainly installed in expensive server and workstation systems. Under the 32-bit operating systems used on these systems (e.g. Windows NT or OS / 2 ), the Pentium Pro achieved a significantly higher performance than a Pentium processor with the same clock speed. The L2 cache operated with the internal processor clock was also responsible for this. In the role of the high-end processor, it was later replaced by the Xeon processor line.
Actually, the Pentium Pro was supposed to replace the Pentium after 1995. However, since production had a high scrap rate (there were problems with the onchip cache in particular), Intel was unable to reduce the price so much that the Pentium Pro was widely used. Instead, the Pentium II was finally developed as the successor to the Pentium . In this case, the processor core and cache are separated.
The Pentium Pro is currently attracting a greater amount of attention, especially at Internet auction portals. Because of its significant gold content, high amounts are offered for its recycling properties. The sales proceeds to be achieved are usually based on the daily gold price.
Contrary to what the name suggests, the architecture of the Pentium Pro differs significantly from that of the earlier Pentium processor. The Pentium Pro contained several important new concepts, such as a RISC core. So it was no longer a pure CISC processor, but rather a kind of hybrid. In addition, with the " out-of-order execution " a concept was introduced that increased the performance potential. While the Pentium processor core executes x86 code natively, the Pentium Pro processor core contains three RISC pipelines working in parallel , which translate the underlying x86 code into RISC commands using three decoder units. This program code modified inside the processor can be distributed more efficiently to the pipelines, which enables better parallelism of instruction processing. The core of the Pentium Pro is the P6 processor core , which is later used in a modified form in the Pentium II , Pentium III , Pentium M and finally in the current Intel Core architecture. The P6 architecture, which laid the foundation for the 686 classification, was the most important step in the development of x86 processors since the 386 was introduced as a 32-bit CPU with its MMU .
The 2nd level cache (L2 cache) and processor core are located in the same processor housing on two (or three in the 1024 KiB model) separate dies , connected by bond wires. There are versions with 256, 512 and 1024 KiB L2 cache. The processor, which is only available for socket 8 , was produced with clock frequencies of 150, 166, 180 and 200 MHz.
The processor accesses main memory and other system components via a GTL + bus . It is possible to operate four processors on one processor bus without further components . Bridge components and other tricks are required for more processors. Such servers were produced by HP (Netserver LX Pro8 - eight processors) and ALR (Revolution 6x6 - six processors) , among others . This made the Pentium Pro the first real server processor from Intel.
The Pentium Pro family also received an overdrive processor that was specified with 300/60 or 333/66 MHz. The core of this was a Pentium II with 512 KiB L2 cache, which, unlike the Pentium II, also ran at full processor speed. These overdrive processors have only been approved by the manufacturer for two-processor systems, since a maximum of two processors can be used with the Pentium II.
- L1 cache: 8 + 8 KiB (data + instructions)
- L2 cache with full CPU clock:
- 256 KiB L2 cache (all clock frequencies except 166 MHz)
- 512 KiB L2 cache (166 and 200 MHz)
- 1024 KiB L2 cache (only 200 MHz)
- Socket 8 , GTL + with 60 and 66 MHz front side bus
- Core Voltage (VCore): 3.3V
- Release date: November 1, 1995, August 18, 1997 (1024 KiB L2 cache)
- Manufacturing technology CPU: 0.5 µm (150 MHz) and 0.35 µm (166–200 MHz)
- Manufacturing technology L2 cache: 0.5 µm (256 KiB L2 cache) and 0.35 µm (512 and 1024 KiB L2 cache)
Die-size CPU (with 5.5 million transistors ):
- 0.50 µm: 306 mm²
- 0.35 µm: 196 mm²
- The size of the L2 cache:
- 0.50 µm / 256 KiB L2 cache: 202 mm² with 15.5 million transistors
- 0.35 µm / 512 KiB L2 cache: 242 mm² with 31.0 million transistors (double values in each case with 1024 KiB L2 cache)
- Clock rates: 150 to 200 MHz
- 256 KiB L2 cache, 66 MHz FSB: 133 MHz ( engineering sample )
- 256 KiB L2 cache, 60 MHz FSB: 150 and 180 MHz
- 256 KiB L2 cache, 66 MHz FSB: 200 MHz
- 512 KiB L2 cache, 66 MHz FSB: 166 and 200 MHz
- 1024 KiB L2 cache, 66 MHz FSB: 200 MHz
Pentium II Overdrive for Pentium Pro P6T
- Implementation date: August 24, 1998
- Introductory price: $ 599
- Base 8
- Clock frequency (s):
- 300 MHz bus clock 5 × 60 MHz
- 333 MHz bus clock rate 5 × 66 MHz
- Internal L1 cache:
- 16 + 16 KiB (data + instructions)
- External L2 cache with full CPU clock:
- 512 KiB L2 cache
- Bus width:
- Data bus: 64 bit
- Address bus: 36 bits
- Transistors / manufacturing technology:
- Addressable memory: 64 GiB
- Virtual memory : 64 TiB
- Georg Schnurer: Next Exit: Mendocino Intel's new processors: Celeron 300A, Celeron 333, Pentium-II-450 and Pentium-II-Overdrive-333 . In: c't 18/98 . c't. P. 20. Archived from the original on May 28, 2005. Retrieved March 13, 2011.
- Specification Update for the Pentium II Processor, page 15, note 3 ( Memento of the original from August 24, 2011 on WebCite ) Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. (PDF; 641 kB)