Intel 8085

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Intel P8085
Production:	1976 to 1990s
Producers: Intel AMD Mitsubishi NEC OKI Siemens Toshiba Tundra Semiconductor
Processor clock:	2 MHz to 6 MHz
Manufacturing :	3 µm, NMOS or enhanced NMOS
Instruction set :	Intel 8 bit
Base:	40-pin DIP

The Intel 8085 is a 1976 introduced 8-bit - microprocessor from Intel . As the successor to the Intel 8080 , it was binary-compatible with it , but integrated the clock generator ( 8224 ) and bus controller ( 8228 ) and had more powerful interrupt handling. The 5 in the name referred to the fact that the processor only needed a 5-volt operating voltage. The Intel 8085 competed on the market with the Zilog Z80 , which was released in the same year and which was also binary downward compatible with the Intel 8080. The chip was used in various CP / M computers, in the training of electronics engineers and as a microcontroller in office typewriters, oscilloscopes and also in the rover of the Pathfinder Mars probe .

Technical specifications

Intel 8085 : Function Block Diagram

• Clock frequency: 5 MHz (other versions with 2 MHz, 3 MHz or 6 MHz)
• Number of transistors: 6500 with 3 µm structure size
• Data bus: 8 bit
• Address bus: 16 bit
• in the AH version 20% less power consumption compared to the normal 8085
• Directly addressable memory of 64  KiB
• 1.3 µs command cycle (0.8 µs for the 8085AH-2 / 0.67 µs for the 8085AH-1)
• 4 vectorized interrupt inputs (one of which cannot be masked and another is an 8080A compatible interrupt)
• binary 8-bit and 16-bit addition, support of 8-bit BCD addition and subtraction (DAA command)
• 40-pin DIL package

In addition to the Intel original, the processor is also manufactured by other manufacturers, some with improved properties. The fastest 8085 processor with 8 MHz comes from the US company Tundra Semiconductor .

construction

Terminal assignment and function

• 

  Terminal assignment

Designation (symbol)	Pin code	Input (E), output (A)	function
A8 - A15: (A H )	21-28	A.	Address bus 8 higher bits of the memory or port address
AD0 - AD7: (A L or D0 - D7)	12-19	I / O	Multiplexed address and data bus (time division multiplexer) 1st clock period of a cycle → low byte of an address 2nd and 3rd clock period → data bus
ALE	30th	A.	Address latch enable, address memory enable Signal 1: AD0 – AD7 have address, is active on the first clock cycle during the first machine cycle. This frees up the address buffer.
S0, S1	29, 33	A.	Machine status signals, display of the operating status of the CPU S1 S0 Operating condition 0 0 Wait through HOLD 0 1 Write operand 1 0 Read operand 1 1 Get command code defines the current machine cycle together with IO / M
IO / M	34	A.	Input-Output / Memory, I / O port access / memory access Differentiates between memory and I / O port access 0 → memory access 1 → I / O port access
RD	32	A.	Read, read (low active) 0 → CPU has released the data bus and is waiting for data from the memory or input port 0 ↑ 1 (rising edge) → CPU takes over the data from the data bus
WR	31	A.	Write, write (low active) 0 → CPU indicates that valid data is on the data bus
READY	35	E.	Ready, readiness 1 → memory or port blocks are ready for data transfer 0 → CPU is waiting with write or read cycle
HOLD	39	E.	Hold, stop 1 → another unit requests the buses, CPU releases the bus as soon as the current bus operation has ended.
HLDA	38	A.	Hold Acknowledge, confirmation of the HOLD status HLDA ← 0 if HOLD request == 0 Half a clock period later, the CPU takes over the bus again.
INTR	10	E.	Interrupt request, general interrupt input for triggering program interruptions from external signals, is blocked or enabled by software
INTA	11	A.	Interrupt Acknowledge, interruption acceptance is used instead of RD after acceptance of an INTR → activation of an interrupt module
RST5.5 RST6.5 RST7.5	9 8 7	E.	Restart interrupts, restart interruptions that can be masked by the SIM and DI commands. Alarm message at 0-1 transition. Here you branch to 3Ch. RST7.5 highest priority of the RSTs, RST5.5 the lowest.
TRAP	6th	E.	Restart interrupt input that cannot be masked
RESIN	36	E.	Reset input, reset input A reset sets the program counter to zero. The HLDA and HOLD flip-flops are also reset. During the reset, data, address and message lines are switched to high resistance. Since this is an asynchronous line, the internal registers can get into an undefined state.
RESOUT	3	A.	Reset output, system reset signal Can be used as a system reset . This signal is synchronized with the processor clock.
X1, X2	1, 2	E.	Clock input
CLK	37	A.	Clock, clock output for use as a system clock. This is half as high as that set at X1, X2
SID	5	E.	Serial Input Data, input for serial data transmission by executing the RIM command, the value is transferred to the accumulator.
SOD	4th	A.	Serial Output Data, output for serial data transmission serial data output, is set or reset by a SIM command.
V CC +5 V	40		Supply voltage (+5 V)
V SS GND	20th		Ground (0 V)

register

The 8-bit register may be taken together for 16-bit instructions to register pairs, these are A / FLAG , B / C , D / E and H / L . The formation of the register pairs is important for the stack commands PUSH and POP and for addressing and address calculation commands .

register
Reg	Function / meaning
A.	Accumulator (8 bit)
B.	general register (8 bit)
C.	general register (8 bit)
D.	general register (8 bit)
E.	general register (8 bit)
H	general register (8 bit)
L.	general register (8 bit)
FLAG	Status register (8 bit)
INT	Interrupt register (8 bit)
IC	Command counter (16 bit)
SP	Stack pointer (16 bit)

The general registers B , C , D and E are essentially used for the logical and arithmetic 8-bit operations, which are also possible with the registers H and L , but should be avoided. The last-mentioned registers play a special role in 16-bit operations. The results of most operations are in the accumulator A .

Register pairs

The register pairs have special tasks depending on the type of addressing. The register pairs BC , DE and 'HL' can be used to read or write data from the main memory to the accumulator A in indexed addressing . In addition to the accumulator, the HL pair allows the use of all 8-bit registers A, B, C, D, H or L as source or destination. Further commands allow the direct exchange of the contents of the register pairs DE and HL , the exchange of the contents of the current top of the stack (SP + 1) (SP) with HL , the contents of HL in the stack pointer and also the contents of HL in the instruction counter . The register pairs can be incremented , decremented and added to the register pair HL .

The technology with the register pairs was significantly expanded in the successor model 8086 .

Status register

Five of the eight bits are occupied in the status register. In the case of conditional jumps and calls, these have the task of deciding whether a jump or call condition is fulfilled. These are in detail N (negative) or S (sign), Z (zero - zero), H (half carry - half carry) or AC (auxiliary carry - auxiliary carry), P (parity - parity) and C (carry - Transfer).

Status register
7th	6th	5	4th	3	2	1	0
N / S	Z	-	H / AC	-	P	-	C.

The bits are set for all logical and arithmetic 8-bit operations, but not for copy and exchange commands. Of the 16-bit commands, only the addition of a register pair to the H / L pair sets the carry bit. The absence of the C bit (carry) is important for increment and decrement commands, for 8-bit operations an overflow can only be checked with the Z-bit (zero), for 16-bit operations only with subsequent OR commands .

Interrupt register

Interrupt register (write and read)
7th	6th	5	4th	3	2	1	0
-	0	-	R7.5	MSE	M7.5	M6.5	M5.5
-	I7.5	I6.5	I5.5	INTE	M7.5	M6.5	M5.5

The assignment of the interrupt register depends on write or read access and the operating mode. The register is mainly used to query and check interrupt statuses and to mask (block) individual interrupts. When writing (SIM command) to the register, bit 6 must always be 0 in order to change the register; in addition, bit 3 (MSE) must be set to 1 in order to take over the interrupt masking in bits 0 to 2.

Interrupts and reset

Hardware interrupts
Int.	Function / meaning
TRAP	(Pin 6) - positive edge triggered
RST 5.5	(Pin 9) - positive level triggered
RST 6.5	(Pin 8) - positive level triggered
RST 7.5	(Pin 7) - positive edge triggered
/ RESIN	(Pin 36) - negative level triggered

Interrupt vectors
address	Tripping
0000h	RESIN /  RST 0
0008h	RST 1
0010h	RST 2
0018h	RST 3
0020h	RST 4
0024h	TRAP
0028h	RST 5
002Ch	RST 5.5
0030h	RST 6
0034h	RST 6.5
0038h	RST 7
003Ch	RST 7.5
italic  = software interrupt

Compared to the predecessor 8080, the interrupt control has been significantly expanded. In addition to the original interrupt (controlled by the interrupt controller), the 8085 has four additional interrupt inputs. The vectorized interrupts and the reset control fixed addresses in the 8085, a concept that was abandoned with the successor types. Starting with the 8086 , the interrupt addresses are stored in a table in the first 1024 bytes.

addressing

The 8085 has an address space of 64 KBytes for memory access and 256 addresses for port access. The distinction between storage and access port is an output IO / M regulated at port accesses a here is H to, during memory accesses a L . A special feature is that the port address is available at both AD0 to AD7 and A8 to A15 for port access . The low-order 8 bits of the address are multiplexed together with the data bus, which means that they share the same connections AD0 to AD7 . The more significant 8 bits have their own connections A8 to A15 . To indicate that a valid address is present on the bus, the processor outputs at the output ALE ( A ddress L atch e nable) a H from. The address can then be temporarily stored in an external memory; a negative edge-triggered or positive pulse-triggered external memory module (usually a D flip-flop ) takes over the content of AD0 to AD7 and outputs this to the low-order eight bits of the pure address bus. In some circuits, the higher-order address byte A8 to A15 is also buffered to improve the timing , even if this is actually not absolutely necessary for the 8085.

The status of the current machine cycle is also output via outputs S0 and S1 (see table above). External modules can be used to set up an address extension, but this does not come close to the segment control of the successor models.

Machine commands

Schematic structure of a machine command

Command structure

An assembler program consists of a sequence of 8-bit commands, in exceptional cases also commands that consist of 2 consecutive bytes. The processing is always carried out sequentially. With a word length of 8 bits, a maximum of 256 different commands are possible, of which only 246 are implemented on the 8085. The first byte of every command contains the operation code (op code), i.e. it is the operator. Often the operand, e.g. If, for example, the accumulator is already contained implicitly, the entire instruction is only one byte long. The command can also be 2 or 3 bytes long:

• 1-byte command: Operation code only
• 2-byte command: operation code + operand (8-bit constant or 8-bit port address)
• 3-byte command: operation code + operand (16-bit constant or 16-bit address).

The instruction sequence in the microprocessor corresponds to the Von Neumann scheme. First, the command to which the contents of the command counter register (program counter, PC, IC) point is fetched and stored in the command decoder. There it is then decoded.

Processing steps of a machine command of the 8085

A command requires 1 to 5 machine cycles (machine cycle, operation cycles) M1 - M5 A machine cycle consists of 3 to 6 clock cycles (states, operation steps) T1 - T6

Depending on the command, a different number of machine cycles are processed. This is recognized in the first machine cycle (command call, FETCH cycle).

Command cycles, machine cycles, clock cycles

The time span for a machine cycle is around 3–6 cycles with "old" microprocessors. Typical machine cycles that can occur within a command cycle are:

1. Command call (OPCODE fetch)
2. Read memory (Memory Read)
3. Write memory (Memory Write)
4. Read stack memory (Stack pop) = read memory twice
5. Write stack memory (stack push) = write memory twice
6. Input
7. Output

Instruction set

Mnemonic	Bytes	Bars	Function of the command
Transfer orders
Register by register
MOV r1, r2	1	04th	r1, r2 = A, B, C, D, E, H, L: Load register r1 with the content of register r2.
XCHG	1	04th	Swap contents of register pairs (D, E) and (H, L)
XTHL	1	16	Swap the content of the register pair (H, L) and the content of the word that is addressed by the stack pointer.
SPHL	1	06th	Load the stack pointer with the contents of the register pair (H, L).
Memory, peripherals according to register
MOV r1, M	1	07th	Load register r1 with the content of the memory byte that is addressed by the content of the register pair (H, L).
LDA adr	3	13	Load the accumulator with the content of the address adr.
LDAX rp	1	07th	rp = B, D Load the accumulator with the content of the memory cell which is addressed by the content of the register pair rp.
LHLD adr	3	16	Load register pair (H, L) with the content of the address adr and (adr + 1)
POP rp	1	10	rp = B, D, H, PSW: register pair rp is loaded with the word that is addressed by the stack pointer
IN no	2	10	The accumulator is loaded with the content of the input channel (number no <256)
Constant after register pair
LXI rp, adr	3	10	rp = B, D, H, SP Load register pair rp with value adr.
Register according to memory, peripherals
MOV M, r1	1	07th	r1 = A; B; C; D; E; H or L: Store the content of register r1 in the memory location that is addressed by the content of the register pair (H, L).
STA adr	3	13	Save the accumulator contents under address adr
STAX rp	1	07th	rp = B, D: store the accumulator in the byte which is addressed by the contents of the register pair rp.
SHLD adr	3	16	Save register pair (H, L) under address adr and (adr +1).
PUSH rp	1	12	rp = B, D, H, PSW The content of the register pair rp is transferred to the word that is addressed by the stack pointer.
OUT no	2	10	The accumulator is output on the output channel (number no <256).
Constant after register, memory
MVI M, const	2	10	Load the memory location that is addressed by the contents of the register pair (H, L) with the constant (const = constant <256)
MVI r1, const	2	07th	r1 = A, B, C, D, E, G, H or L: Load register r1 with the constant (const <256)
Arithmetic commands
INR r1	1	04th	r1 = A, B, C, D, E, F, H or L: 1 is added to the content of register r1.
INR M	1	10	1 is added to the content of the byte addressed by the register pair (H, L).
DCR r1	1	04th	r1 = A, B, C, D, E, F, H or L: 1 is subtracted from the content of register r1.
DCR M	1	10	1 is subtracted from the content of the byte addressed by the register pair (H, L).
INX rp	1	06th	rp = B, D, H, SP: The content of the register pair is increased by 1.
DCX rp	1	06th	rp = B, D, H, SP: The content of the register pair rp is decreased by 1.
ADD r1	1	04th	r1 = A, B, C, D, E, F, H or L: The content of r1 is added to the content of the accumulator.
ADD M	1	07th	The content of the memory byte, which is addressed by the content of the register pair (H, L), is added to the accumulator.
ADC r1	1	04th	r1 = A, B, C, D, E, F, H or L: The content of register r1 and the content of the carry bit are added to the accumulator
ADC M	1	07th	The content of the memory byte addressed by the content of the register pair (H, L) and the content of the carry bit are added to the content of the accumulator.
DAD rp	1	10	rp = B, D, H, SP: The content of the register pair rp and the content of the register pair (H, L) are added. The result is in (H, L).
SUB r1	1	04th	r1 = A, B, C, D, E, H or L: the content of the register pair is subtracted from the accumulator.
SUB M	1	07th	The content of the memory byte, which is addressed by the content of the register pair (H, L), is subtracted from the accumulator.
SBB r1	1	04th	r1 = A, B, C, D, E, H or L: The content of register r1 and the content of the carry bit are subtracted from the accumulator content.
SBB M	1	07th	The content of the memory byte addressed by the register pair (H, L) and the content of the carry bit are subtracted from the accumulator
ADI const	2	07th	Constant (const <256) is added to the content of the accumulator.
ACI const	2	07th	The constant (const <256) and the carry bit are added to the accumulator content.
SUI const	2	07th	Constant (const <256) is subtracted from the content of the accumulator.
SBI const	2	07th	The constant (const <256) and the carry bit are subtracted from the accumulator content.
DAA	1	07th	The contents of the accumulator are converted into a two-digit number.
Logical operations
CMA	1	04th	The content of the accumulator is negated.
ANA r1	1	04th	r1 = A, B, C, D, E, H or L: Accumulator and the content of register r1 are ANDed.
ANA M	1	07th	The contents of the byte addressed by the register pair (H, L) are ANDed with the accumulator.
ANI const	2	07th	The accumulator is linked with the constant (const <256) AND.
ORA r1	1	04th	r1 = A, B, C, D, E, H or L: The contents of the accumulator are ORed with the contents of the register r1.
ORA M	1	07th	The content of the byte addressed via register pair (H, L) is ORed with the content of the accumulator.
ORI const	2	07th	Accumulator content is ORed with the constant (const <256).
XRA r1	1	04th	Accumulator is linked with the content of register r1 EXCLUSIVE-OR.
XRA M	1	07th	The byte addressed via registers (H, L) is EXCLUSIVE-ORed with the accumulator content.
XRI const	2	07th	The accumulator is linked with the constant (const <256) EXCLUSIVE-OR.
CMP r1	1	04th	Accumulator is compared with the contents of the register. If the values ​​are the same, the zero flag is set.
CMP M	1	07th	The accumulator is compared with the content of the byte addressed by the register pair (H, L).
CPI const	2	07th	Accumulator is compared with the constant (const <256).
Register instructions
Rotate the accumulator
RLC	1	04th	The content of the accumulator is cyclically shifted by 1 bit to the left. Bit 2 ^ 7 is written into the carry bit. Bit 2 ^ 0 = bit 2 ^ 7
RRC	1	04th	The contents of the accumulator are cyclically shifted by 1 bit to the right. Bit 2 ^ 0 is written into the carry bit. Bit 2 ^ 7 = bit 2 ^ 0
RAL	1	04th	The content of the accumulator is cyclically shifted by 1 bit to the left. Bit 2 ^ 7 is written into the carry bit and the carry bit into bit 2 ^ 0.
RAR	1	04th	The contents of the accumulator are cyclically shifted by 1 bit to the right. Bit 2 ^ 0 is written in the carry bit and the carry bit in bit 2 ^ 7.
Carry-bit instructions
CMC	1	04th	Carry bit is negated.
STC	1	04th	Carry bit is set.
Jump commands
Unconditional jumps
PCHL	1	06th	The program is continued at the address in the register pair (H, L).
JMP adr	3	10	The program is continued at the address adr
Conditional jumps
JC adr	3	07/10	If the carry bit = 1, the program is continued at address adr.
JNC adr	3	07/10	If the carry bit = 0, the program is continued at address adr
JZ adr	3	07/10	If the zero bit = 1, the program is continued at address adr
JNZ adr	3	07/10	If the zero bit = 0, the program is continued at address adr
JM adr	3	07/10	If the sign bit = 1, the program is continued at address adr
JP adr	3	07/10	If sign bit = 0, the program is continued at address adr
JPE adr	3	07/10	If the parity bit = 1, the program is continued at address adr
JPO adr	3	07/10	If the parity bit = 0, the program is continued at address adr
Subroutine handling
Subroutine calls
CALL adr	3	18th	The program is continued at the address adr
CC adr	3	09/18	If the carry bit = 1, the program is continued at address adr
CNC adr	3	09/18	If the carry bit = 0, the program is continued at address adr
CZ adr	3	09/18	If the zero bit = 1, the program is continued at address adr
CNZ adr	3	09/18	If the zero bit = 0, the program is continued at address adr
CM adr	3	09/18	If Sign -Bit = 1, the program is continued at address adr
CP adr	3	09/18	If Sign -Bit = 0, the program is continued at address adr
CPE adr	3	09/18	If the parity bit = 1, the program is continued at address adr
CPO adr	3	09/18	If the parity bit = 0, the program is continued at address adr
RST const	1	12	The program is continued at the address 8x const (const = 0-7)
Return commands
RET	1	10	The program is continued at the address that is in the word that is addressed via the stack pointer.
RC	1	06/12	Carry bit = 1, the program is continued at the address that is in the word addressed via the stack pointer.
RNC	1	06/12	Carry bit = 0 the program is continued at the address that is in the word addressed via the stack pointer.
RZ	1	06/12	Zero -Bit = 1 the program is continued at the address that is in the word addressed via the stack pointer.
RNZ	1	06/12	Zero -bit = 0 the program is continued at the address that is in the word addressed via the stack pointer.
RM	1	06/12	Sign -Bit = 1 the program is continued at the address that is in the word addressed via the stack pointer.
RP	1	06/12	Sign -Bit = 0 the program is continued at the address that is in the word addressed via the stack pointer.
RPE	1	06/12	Parity bit = 1, the program is continued at the address that is in the word addressed via the stack pointer.
RPO	1	06/12	Parity bit = 0, the program is continued at the address that is in the word addressed via the stack pointer.
Program interruption
EGG	1	04th	Interrupt flip-flop is set; The microprocessor can accept an interrupt request
DI	1	04th	The interrupt flip-flop is reset. The microprocessor ignores interrupt requests.
Mask bit commands
RIM	1	04th	Read interrupt mask and serial input into accumulator.
SIM	1	04th	Set interrupt mask and serial output.
Other command
LDS	1	05	Program stops until an interrupt request occurs.
NOP	1	04th	No operation
Mnemonic	Bytes	Bars	Function of the command

Sample program

Simple program with input and output

 ; Ein Kommentar wird mit einem Semikolon bzw. Strichpunkt eingeleitet, der Text dahinter wird vom Assembler ignoriert
 mark: ; eine Marke wird mit einem Doppelpunkt gekennzeichnet

 star: IN 01       ;Einlesen des Ports 01
       OUT 02      ;Ausgabe am Port 02
       JMP star    ;Ruecksprung zum Programmanfang

More complex program

This program shows a small running light. It can be switched ON and OFF with bit D7 on the input module. With bit D6 the direction of rotation is determined (right or left) and with bit D0 you can choose between 2 running speeds. Pause should be set to 0 and bit D7 to 1.

 ;Hauptprogramm
       MVI B,01    ;Anfangswert für Rotation
 mei:  IN 01       ;Ein? (Bit D7=1?)
       ANI 80      ;Bitmaske für D7
       JZ mei      ;-->MEI, wenn nicht "EIN"
       MOV A,B     ;Lauflicht ansteuern
       OUT 02
       IN 01       ;Linksrotation? (Bit D6=1?)
       ANI 40      ;Bitmaske für D6
       JZ rr       ;-->RR, wenn keine Linksrotation
       MOV A,B
       RLC         ;nächste Linksrotation
       MOV B,A
 mv:   IN 01       ;schnelle Rotation? (Bit D0=1?)
       ANI 01      ;Bitmaske für Bit D0
       JZ ze2      ;-->ZE2, wenn langsam
       CALL ze1    ;sonst Unterprogramm ZE1 aufrufen
       JMP mei

 ;Rechtsrotation
 rr:   MOV A,B
       RRC         ;nächste Rechtsrotation
       MOV B,A
       JMP mv

 ;Zeitschleife 1
 ze1:  LXI D,0001  ;Z laden
 mz1:  DCX D       ;Z:=Z-1
       MOV A,D     ;Z=0?
       ORA E
       JNZ mz1     ;-->MZ1, wenn nicht 0
       RET         ;Rücksprung…

 ;Zeitschleife 2
 ze2:  LXI D,0006  ;Z laden
 mz2:  DCR D       ;Z:=Z-1
       MOV A,D     ;Z=0?
       ORA E
       JNZ mz2     ;-->MZ2, wenn nicht 0
       JMP mei

Output program to memory

 ;Tabellen:
       ;tab1
       ORA 0e100   ;Tabellenadresse
       DB 01,02,04,08,10,20,40,80,00
       ;tab2:
       ORG 0e200   ;Tabellenadresse
       DB 01,03,07,0F,1F,3F,7F,0FF,00

 ;Hauptprogramm
       ORA 0e000   ;Startadresse
       LXI SP,0fc32;Stackpointer mit der Adresse fc32 laden
                   ;eine Null muss bei Hex-Buchstaben vorangestellt werden
       LC          ;Labeltabelle löschen

 ;Programmfunktion:
                   ;Marken bzw. Labels werden mit einem Doppelpunkt initialisiert
 star: IN 01       ;Der Hex-Wert vom Eingabe Port mit der
                   ;Adresse 01 wird in den Akkumulator geladen
       ANI 01      ;UND-Verknüpfung des Hex-Wertes 01 mit dem Akku
       JZ sch1     ;Wenn das Zero-Flag gesetzt ist, springe zur Marke "sch1"
       JNZ sch2    ;Wenn das Zero-Flag nicht gesetzt ist, springe zur Marke "sch2"

 ;1. Unterprogramm
 sch1: LXI H,0e100 ;Lädt das Registerpaar HL mit der Adresse e100
 loo1: MOV A,M     ;Der Wert der in der Speicherzelle steht, welche durch das Registerpaar
                   ;HL adressiert ist in den Akku
       ORA A       ;ODER-Verknüpfung des Akkus mit sich selbst
       JZ star     ;Wenn das Zero-Flag gesetzt ist, springe zur Marke "star"
       OUT 02      ;Der Inhalt des Akkus wird an den Ausgabeport übergeben
       INX H       ;Die Tabellenadresse in HL wird um den Wert 1 erhöht
       CALL 0895   ;UP-Aufruf
                   ;UP für eine Zeitschleife von 0,2 Sekunden
       JMP loo1    ;Programmbereich wiederholen, springe nach "loo1"

 ;2. Unterprogramm
 sch2: LXI H,0e200 ;Lädt das Registerpaar HL mit der Adresse E200
 loo2: MOV A,M     ;Der Wert der in der Speicherzelle steht, welche durch das Registerpaar
                   ;HL adressiert ist in den Akku
       ORA A       ;ODER-Verknüpfung des Akkus mit sich selbst
       JZ star     ;Wenn das Zero-Flag gesetzt ist, springe zur Marke "star"
       OUT 02      ;Der Inhalt des Akkus wird an den Ausgabeport übergeben
       INX H       ;Die Tabellenadresse in HL wird um den Wert 1 erhöht
       CALL 0895   ;UP-Aufruf
                   ;UP für eine Zeitschleife von 0,2 Sekunden
       JMP loo2    ;Programmbereich wiederholen, springe nach "loo2"

 stop: JMP stop    ;Endlosschleife, um bei einem Fehler das weiterlaufen des
                   ;Programmes zu verhindern.

simulation

For the Microsoft Windows and Linux operating systems there is, among other things, the free and open source simulator GNUSim8085 , which is available under the GNU General Public License .

Peripheral modules (selection)

• Intel 8251 serial interface
• Intel 8253 , Intel 8254 counter / timer
• Intel 8255 parallel interface
• Intel 8257 , Intel 8237 DMA controllers
• Intel 8259 interrupt control

Web links

Commons : Intel 8085  - collection of pictures, videos and audio files

• Intel 8085 - Collectors website with lots of pictures
• Intel 8085 microprocessor family . on CPU-World.com (English)

Individual evidence

1. ^ JPL Robotics: Project: Pathfinder. In: www-robotics.jpl.nasa.gov. Retrieved July 11, 2016 .