Intel Atom microarchitecture

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Intel Atom microarchitecture is a collective term for various energy-saving main processors - microarchitectures made by Intel . The energy efficiency is achieved, among other things, by a lower complexity of the microarchitectures compared to high-performance designs. The Atom microarchitecture family currently comprises the generations Bonnell , Saltwell , Silvermont , Airmont , Goldmont and Goldmont Plus . It was originally only used in Intel Atom branded products .


From 2007 it became clear that Intel needed an energy-saving, inexpensive to implement microarchitecture for use in nettops and netbooks . A decision was made in favor of “simplified” CPU cores based on their own x86-64 instruction set, for which a very wide range of software already existed. Later, Mobile internet devices (MID), smartphones and tablets and Ultrabooks and micro servers added as applications. However, it was not possible to develop a system-on-a-chip with an integrated cellular modem .


Bonnell and Saltwell

Release Micro-
Tick ​​/ Tock
 2008 Bonnell 045 nm New development
 2011 Saltwell 032 nm Shrink
 2013 Silvermont 022 nm new out-of-order architecture
 2014 Airmont 014 nm Shrink
 2016 Goldmont 014 nm new architecture
 2017 Goldmont Plus 014 nm Optimization of the Goldmont design

In 2008, Intel presented the first implementations of the Bonnell generation . In Bonnell is a micro-architecture with in-order execution . It thus resembles the micro-architecture of the IDT WinChip , VIA C3 and VIA C7 processors from Centaur Technology ; At Intel itself, the micro-architecture developed for the Intel Pentium- 1 family was the last draft of its kind. Modern out-of-order architectures such as the Intel Core micro -architecture or AMD64 achieve their high per-clock performance (IPC) with many additional functions such as register renaming or speculative execution . For the implementation of these functions, however, many additional transistors are required, which, in addition to increasing the die size and thus the production costs, are also responsible for an increase in the power loss. An in-order architecture dispenses with such functions and processes all commands strictly in sequence; the IPC is therefore considerably lower. However, this enables energy-saving processors with a very small die size, which are therefore also cheaper to produce. The disadvantage of the lower performance plays a subordinate role in the field of application of these processors. Bonnell was developed to be manufactured using the 45 nm process. The shrink to 32 nm followed in 2011 and was named Saltwell .

In some implementations of the Bonnell and Saltwell generations, Intel counteracts the low IPC for multithreaded programs with the hyper-threading already known from the NetBurst architecture (e.g. Intel Pentium 4) . Hyper-Threading or Simultaneous Multithreading enables a better utilization of the execution units of a processor, whereby the execution speed can be improved depending on the application.

Silvermont and Airmont

For the Silvermont generation (from 2013), Intel changed the micro-architecture towards out-of-order execution. As a result of the out-of-order instruction execution, machine instructions in the execution units of the processor can be executed in a different order than they are in the program code. This allows the stages of the pipeline to be better utilized. Due to the requirement that the result of these operations must be the same as when executing in the program sequence, out-of-order command execution is only possible for command sequences that are not dependent on one another. The out-of-order command execution leads to a higher power consumption and a larger area requirement on the chip, since the corresponding logic has to be implemented in the form of additional transistors. This was one reason it was only introduced with 22nm manufacturing. Compared to the Bonnell generation, the implementation leads to an approximately 30% increase in computing power per thread.

Since the Silvermont generation , Intel has had enough chip area to implement additional processor cores instead of having to rely on Hyper-Threading - multi-core instead of multi-threading. The energy saved by eliminating Hyper-Threading was invested in the out-of-order design, which in turn helped to make optimal use of resources. It turned out that Intel would have required roughly the same chip area for Hyper-Threading in 22 nm production as Silvermont used for the re-order buffer and out-of-order logic, so there wasn't even one small disadvantage from switching from Hyper-Threading to out-of-order instruction execution. Taking into account the fact that most apps for smartphones and tablets are only suitable for multithreading to a limited extent, this is another big improvement, as every program, even if it was only developed for single threading, is out of order -Instruction execution benefits.

While Medfield and earlier platforms use the old FSB infrastructure for coherent on-chip communication, the so-called in-die interface (IDI) from Nehalem and Westmere is used in the new Silvermont-based SoCs.

The shrink to 14 nm followed in 2014 and was named Airmont .


Goldmont continued to be developed on the basis of 14 nm manufacturing technology and was presented in 2016. Goldmont achieves around 50% higher integer computing power than Silvermont . When it comes to encryption and decryption, the new architecture is around 290% faster than its predecessor. The per-MHz processing power of a gold Mont core as is on a par with the ARM Cortex-A72 . The maximum clock frequency is 2.6 GHz. A variant called Denverton (C3xxx model names) with up to 16 cores for use in microservers appears for the first time . SoC variants for smartphones and tablets are no longer being developed because it was not possible to find buyers for them. Other variants are: "Apollo Lake" -CPUs for mobile devices: Pentium N4xxx, N3xxx with processor graphics, desktop CPUs Pentium J4205 and Celeron J3x55 with processor graphics, Embedded (E39xx)

Goldmont Plus

The Goldmont Plus microarchitecture generation introduced in December 2017 can be found in single-chip systems with the Intel code name Gemini Lake . Was implemented Gold Plus Mont far for mobile use in the SoC models Celeron N4000, N4100 and N5000 Pentium Silver. The models Celeron J4005, J4105 and Pentium Silver J5005 are intended for stationary use in desktop computers, for example.

Instruction set

The Atom microarchitecture is basically a 64-bit architecture and can therefore support Intel 64 or AMD64 . With the exception of the Atom processors 230, 330, and N450 to N550 and D410 to D525, the Bonnell implementations are limited to 32 bits. The instruction set extensions MMX , SSE , SSE2 , SSE3 and SSSE3 are implemented. Silvermont also brought support for SSE4.1 , SSE4.2 , POPCNT and AES-NI , but not AVX .

Product implementations

The Bonnell microarchitecture and its shrink Saltwell were only implemented in CPUs and SoCs of the Intel Atom brand . Since the Silvermont generation , the designs have also been used in the Intel Celeron Nxxxx and Jxxxx and Intel Pentium Nxxxx and Jxxxx product lines. Intel also used the Airmont core as the basis for its Intel Xeon Phi series.

See also

Individual evidence

  1. a b c d Frank Riemenschneider: Intel's Silvermont more energy-efficient than ARM? In: , May 16, 2013. ( Memento from March 26, 2014 in the Internet Archive )
  2. Frank Riemenschneider: The microarchitecture of Intel's Silvermont in detail In: , May 22, 2013. ( Memento of March 26, 2014 in the Internet Archive )
  3. Frank Riemenschneider : Intel's "Goldmont" makes "Atom" competitive . In: . June 22, 2017. Retrieved August 22, 2017.
  4. Intel Atom Processor Specifications . Intel. Archived from the original on April 16, 2011. Retrieved on August 28, 2010.


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