VIA C3

from Wikipedia, the free encyclopedia
VIA C3
KL VIA C3 No Goldcap.jpg
Production: since 2001
Producer: TSMC
Processor clock: 700 MHz to 1.2 GHz
FSB cycle: 100 MHz to 133 MHz
L2 cache size: 64 KB
Instruction set : x86
Microarchitecture : RISC
Base: Base 370
Names of the processor cores:
  • Samuel 2 (C5B)
  • Ezra (C5C)
  • Ezra-T (C5N)
  • Nehemiah (C5XL)
  • Nehemiah + (C5P)

The VIA C3 (previously called VIA Cyrix III ) is an x86 processor for Socket 370 from VIA Technologies . The CPUs were developed by Centaur Technology , a subsidiary of VIA Technologies. The C3 series is the successor to the WinChip CPUs from IDT . Centaur CPUs are developed with the focus on the lowest possible production costs. To make this possible, it is necessary that the hold face as small as possible. This inevitably meant that the architecture had to be kept very simple. The C3 CPUs were therefore no performance miracles, but shone through their very low power consumption and low heat generation, as well as hardly any bugs. The CPU cores are also partly used in the Eden series in the Eden ESP and Eden-N models.

Models

Samuel 2 (C5B)

The Centaur Samuel (C5A) was launched on the market as VIA Cyrix III in mid-2000, and at the beginning of 2001 followed with the Samuel 2, the now called VIA C3 with an on-die L2 cache of 64 KB. This additional cache was made possible because the structure size could be reduced to 0.15 µm by shrinking .

Ezra (C5C)

The Ezra is nothing more than another shrink of Samuel / Samuel 2 to 0.13 µm. The Ezra was the first CPU to be mass-produced in 0.13 µm. This time the smaller die area was not used to expand the cache.

Ezra-T (C5N)

Ezra-T is only a modified version of the Ezra and enabled the use of the bus protocol changed by Intel for the Tualatin and is only to be seen as a compatibility measure. The Ezra has been completely replaced by the Ezra-T.

Nehemiah (C5XL)

The first noteworthy revision was the Nehemiah in early 2003. With this CPU, Centaur increased the speed of the FPU drastically and made it more competitive. In addition, 3DNow! replaced by SSE , which is better supported by software. Centaur has completely revised the CPU so that 100% binary compatibility with the Intel Pentium Pro and thus also with the Pentium II , Pentium III and Pentium 4 could finally be achieved. Before that, it was necessary to compile software for C3 CPUs for Pentium architecture, as the C3 did not support the family of cmov instructions introduced with the i686 standard . cmov ( conditional move , used to avoid jumps) was perhaps the most important innovation in the i686 standard, but it was still an optional part of the i686 specification. In purely formal terms, the C3 was therefore i686-compatible. In practice, however, no compiler differentiated between “i686 with cmov” and “i686 without cmov”, so programs compiled for i686 did not run on the C3.

As a special feature, Centaur also built in a hardware random number generator (RNG), i.e. a random number generator that is very useful for crypto applications. Due to these extensive changes (even if one cannot speak of a new architecture), it was assumed in advance that the Nehemiah would not come onto the market as a C3, but as a C4.

Nehemiah + (C5P)

In the old tradition, the Nehemiah + is just a revised Nehemiah, in which even more advanced encryption techniques have been incorporated. It is also used as the processor core in the VIA CoreFusion platform.

Model data

Samuel

  • Code name: C5A

See article VIA Cyrix III

Samuel 2

VIA 1.1GigaPro.
  • Code name: C5B
  • L1 cache: 64 + 64 KB (data + instructions)
  • L2 cache: 64 KB with processor clock
  • MMX , 3DNow! , LongHaul!
  • Socket 370 , GTL + with 100 and 133 MHz front side bus
  • Operating voltage (VCore): 1.60 V.
  • Power consumption ( TDP ): approx. 6 W.
  • Release DATE: March 2001
  • Manufacturing technology: 0.15 µm at TSMC
  • The size: 52 mm² with 15.2 million transistors
  • Clock rates: 700 to 800 MHz

Ezra

Ezra, 866 MHz.
  • Code name: C5C
  • L1 cache: 64 + 64 KB (data + instructions)
  • L2 cache: 64 KB with processor clock
  • MMX , 3DNow! , PowerSaver 3.0
  • Socket 370 , GTL + with 100 and 133 MHz front side bus
  • Operating voltage (VCore): 1.35V
  • Power consumption ( TDP ): approx. 6 W.
  • Release DATE: June 2001
  • Manufacturing technology: 0.13 µm at TSMC
  • The size: 52 mm² with 15.4 million transistors
  • Clock rates: 800, 866 and 933 MHz

Ezra-T

Ezra-T, 933 MHz.
  • Code name: C5N
  • L1 cache: 64 + 64 KB (data + instructions)
  • L2 cache: 64 KB with processor clock
  • MMX , 3DNow! , PowerSaver 3.0
  • Socket 370 , AGTL + with 100 and 133 MHz front side bus
  • Operating voltage (VCore): 1.35 V to 1.45 V.
  • Power consumption ( TDP ): approx. 12 W.
  • Publication date:
  • Manufacturing technology: 0.13 µm at TSMC
  • The size: 56 mm² with 15.5 million transistors
  • Clock rates: 800, 866, 933 and 1000 MHz

Nehemiah

Nehemiah with 1.2 GHz.
  • Code name: C5XL
  • L1 cache: 64 + 64 KB (data + instructions)
  • L2 cache: 64 KB with processor clock
  • MMX , SSE , PowerSaver 3.0 , PadLock -Engine (1 × RNG)
  • Socket 370 , AGTL + with 100 and 133 MHz front side bus
  • Operating voltage (VCore): 1.40 V.
  • Power consumption ( TDP ): 15 W to 18 W
  • Release DATE: Jan 22, 2003
  • Manufacturing technology: 0.13 µm at TSMC
  • The size: 52 mm² with 20.5 million transistors
  • Clock rates: 1,000, 1,066, 1,133 and 1,200 MHz

Nehemiah +

  • Code name: C5P
  • L1 cache: 64 + 64 KB (data + instructions)
  • L2 cache: 64 KB with processor clock
  • MMX , SSE , PowerSaver 3.0 , PadLock -Engine (2 × RNG, 1 × ACE), SMP
  • Socket 370 , AGTL + with 100 and 133 MHz front side bus
  • Operating voltage (VCore): 1.25 V.
  • Power consumption ( TDP ): 12 W to 15 W.
  • Publication date:
  • Manufacturing technology: 0.13 µm at TSMC
  • The size: 47 mm² with 20.4 million transistors
  • Clock rates: 1,000, 1,133 and 1,200 MHz

See also

Web links