Intel Pentium is the brand name of a range of microprocessors and single-chip systems (English. Systems-on-Chip , SoCs ) that were developed by Intel . The mark was first used for a microprocessor in 1993. This appeared as the successor to the successful i486 ; two of the main architects were Uri C. Weiser and John Crawford .
According to the naming scheme previously used by Intel, the successor to the fourth generation x86 processor should actually have been called 80586 or i586 for short . At the end of 1992, however, Intel announced that its new microprocessor development announced at CeBIT 1993 should be called Pentium . The name Pentium was derived from penta ( πεντα ) - the Greek word for "five". Intel justified this choice of name with the impossibility of having numbers protected under trademark law . The competitors Cyrix and AMD used slight variations of the Intel name, namely Cyrix Cx486 and Am486 , to name their clones of the Intel i486 .
After the Pentium brand was launched, Intel also used it for subsequent generations of microprocessor models. Until the introduction of the Core brand in 2006, Pentium was always used to designate models from the upper part of the Intel x86 processor range in terms of performance and price.
The Pentium 1 family
|<< Intel Pentium >>|
Logo for the Intel Pentium MMX
|Production:||1992 to 1999|
|Processor clock:||60 MHz to 300 MHz|
|FSB cycle:||50 MHz to 66 MHz|
|L1 cache size:||16 KiB to 32 KiB|
|Manufacturing :||0.8 µm to 0.25 µm|
|Instruction set :||x86 (16 bit) and x86-32|
Names of the processor cores:
The Pentium microprocessor introduced in 1993 was called the P5 internally at Intel . The design came from the same development team that had developed the 486. This Pentium appeared as the first superscalar CISC - microprocessor in the world. RISC technology was integrated here without losing backward compatibility with the 486.
Compared to the classic RISC design, the 486 has an extended 5-stage pipeline (Fetch, Decode 1, Decode 2, Execute, Write Back). The Pentium also has this extended 5-stage pipeline, but got two execution units, U and V, which could execute certain (pairable) commands superscalar .
The design implements two integer execution units, a floating point execution unit, dynamic jump prediction , separate data and code caches of 8 KB each and a 64-bit wide external data bus with fast burst modes to quickly connect the external cache to be able to. Additional functions were added, such as a system management mode (SMM), hardware-supported performance monitoring and execution tracing. The two pipelines allow the Pentium to have two functional units involved in the execution of instructions work in parallel if the opportunity arises (integer and floating point operations can be carried out largely independently of one another). The dynamic jump prediction compensates for a conceptual disadvantage of the pipeline architecture: if a jump occurs, the results of already processed partial instructions become invalid, which is why the entire contents of the pipeline must be discarded (so-called pipeline flush ). In contrast to the Pentium Pro, the address bus remained 32 bits wide (4 GiB address space).
However, the level 2 cache of the Pentium chipsets at that time did not cover the entire memory area. It was 64 MB for the Intel 430FX / TX / VX chipset, and 512 MB for the Intel 430HX chipset (second tag RAM was then required). Memory above this limit was usable, but slower.
The FDIV bug
It was not until a year and a half after its launch that the Pentium caused a sensation with the FDIV bug - because of its popularity, it was sometimes referred to as a Pentium bug . In addition to the error itself, Intel's handling of this error particularly unsettled many users. Intel initially tried to downplay this bug. Processor models based on the P55C and the following designs are not affected by the FDIV bug.
Variants of the Pentium-1
The P5 Pentium
The first generation of the Pentium, the P5, was presented at CeBIT 1993. The only two representatives of the P5 are the Pentium 60 and the Pentium 66. Both work with a supply voltage of around 5 volts and are inherently not multiprocessing capable. But they already support the MESI protocol to ensure the cache - coherency in multiprocessor mode . Its core - comparable to that of the first 486 processors - is still operated with the same clock frequency as the bus interface . Both CPUs only fit in socket 4 and otherwise differ only insignificantly from their successor, the P54C.
Despite its advanced design, the P5 was not a huge commercial success for Intel. But that was by no means due to a lack of technical qualities; rather, Intel had created an in-house competitor, the i486 processor DX4 clocked at 100 MHz . Complete systems with the DX4 were significantly cheaper to purchase and were hardly inferior to those with a Pentium 60 in terms of computing power . In addition, the DX4 could be retrofitted if a 486 mainboard was already available, which did not provide good starting conditions for the new processor.
Another problem is the supply voltage of around 5 volts. In connection with the then often too tightly dimensioned heat sinks (which were not always necessary at the time of the introduction of the Pentium and therefore not very common) and fans, this leads to a strong heating of the CPU and often even adjacent components on the mainboard (heat conduction via the Conductor tracks made of copper), which usually leads to unstable operation of the computer.
The P54C / P54CS Pentium
The P54C Pentium was presented at CeBIT 1994. It came onto the market first with 90 and 100 MHz, shortly afterwards with 75 MHz and then with 120 MHz. In contrast to the P5, the P54C has an on-chip APIC and is therefore multiprocessor- capable by default. Nevertheless, Intel did not guarantee the functionality of the APIC for all CPUs, which is why versions were also sold that did not support multiprocessor operation. In addition, the P54C has the improved, so-called SL-enhanced power management. The supply voltage could be reduced to 3.3 V.
The P54CS, also known as the Pentium-S, with 133, 150, 166 and 200 MHz followed until 1997. Socket 5 was initially intended for the P54C , and downward compatible Socket 7 from the P54CS onwards . In particular, the Pentium-S with 133 MHz can also be operated unofficially in socket 5, as it does not depend on the properties of socket 7.
Unlike its predecessor, the P5, the P54C became a huge success for Intel. It would take nearly two years for competitive Pentium clones to hit the market. While Intel favored the Pentium, the competition - also successfully - butchered the 486 platform further. AMD and Cyrix continued to bring fast 486 processors onto the market, at the end of 1995 - under the name 5x86 - even those that could compete with a Pentium 75. At that time Intel was already with the Pentium 133. In the course of 1996 AMD countered with the 5k86, the later K5 and Cyrix with the 6x86 . The latter even managed to endanger the then fastest Pentium with its integer computing power. But before the 6x86 could really establish itself, Intel countered again in early 1997 with a further development of the P54C, the P55C.
The P55C Pentium (Pentium MMX)
The P55C was developed at Intel's research and development center in Haifa, Israel. It is the last and most powerful processor from the Pentium 1 family. It was sold under the name Pentium MMX , as it was the first processor to be equipped with Intel's new MMX instruction set extension. The Pentium MMX is available with clock frequencies of 133 MHz (mobile only), 166, 200 and 233 MHz (desktop and mobile) as well as 266 and 300 MHz (mobile only). Since the bus interface of the P55C is operated with 3.3 V, but the CPU core with 2.8 V, it requires a special form of socket 7 , the so-called split-voltage-capable socket 7 , not to be confused with the Super -Socket 7 .
In addition, the P55C has been improved internally. Although it essentially retained the architecture of the P54C, it optimized and supplemented it in many places. The P55C has caches that are twice as large as its predecessors, a significantly improved branch prediction - adopted from the Pentium Pro - four instead of two write buffers and a CPU-internal return stack to accelerate subroutine returns. Its pipelines have also been improved. So they can now also be fed with command combinations (so-called command pairings ) in parallel that were not possible before, and an additional level has been added.
Although the improvements to the pipeline were made mainly because of the addition of the MMX instructions, non-MMX applications also benefit from them. The bottom line is that the improvements result in a significant increase in performance . In non-MMX applications, the P55C is on average around 15 to 20 percent faster than a similarly clocked P54C, with a large part of this increase being attributable to the larger cache.
Versions of the P5-MMX existed as PentiumODPMT (P54CTB, P5-Overdrive-Processor ) which, due to an integrated voltage converter, could also be used on mainboards with Socket 5, i.e. without a split voltage supply.
|Code name||P5||P54C||P54CS (Pentium-S)||P55C||Tillamook *|
(data + instructions)
|8 + 8 KiB||8 + 8 KiB||16 + 16 KiB|
|Manufacturing technology ( µm )||0.80 BiCMOS||0.60 or 0.35 BiCMOS *||0.35 BiCMOS||0.35 CMOS (later 0.28)||0.25 CMOS|
|Number of transistors (million)||3.1||3.3||3.3||4.5||4.5|
|294||148 at 0.6 µm /
91 (later 83) at 0.35 µm
|141 at 0.35 µm /
128 at 0.28 µm
|90 (Intel SmartDie ***
9.063mm x 10.424mm = 94.47mm²)
|base||Base 4||Socket 5 (compatible with 7)||Base 7||Base 7||-|
|casing||CPGA||CPGA / TCP *||CPGA / PPGA / TCP *||CPGA / PPGA / TCP *||TCP / TCP on MMC-1|
|Clock frequency ( MHz )||60||66||75||90||100||120||133||150||166||200||120 *||133 *||150 *||166||200||233||166||200||233||266||300|
|FSB ( MHz )||60||66||50||60||66||60||66||60||66||60||66||60||66||66|
|TDP (max. W)||14.6||16||8 **
7.3 * / **
|14.5 **||15.5 **||?||7.8||8.6||13.1
|March 27–1. Nov
* These are only available as Mobile Pentium or Mobile Pentium MMX for laptops .
** Not TDP, but Max. Active Power Dissipation
*** Intel SmartDie 27315402 (or 273154-002) Mobile Pentium® Processor MMX ™ Technology 0.25 Micron SmartDie® Product Specification
(data + instructions)
|16 + 16 KiB|
|Manufacturing technology (µm)||0.35|
|casing||CPGA with heat sink, fan and voltage regulator|
|Clock frequency (MHz)||125||150||166||150||180||200|
90, 120, 150
100, 133, 166
|TDP (max. W)||15.6||15.6||15.6||18th|
|Manufacturing technology (µm)||0.35||0.25|
|Clock frequency (MHz)||200||233||166||166||166||266||266|
|TDP (max. W)||15.7||17th||4.5||4.1||4.1||7.6||7.6|
Other Intel products from the Pentium brand
The architectures of processors published under the Pentium brand differ fundamentally in some cases (Intel® Pentium® III Processor 1.13 GHz and Intel® Pentium® 4 Processor 1.30 GHz), on the other hand there are processors whose cores are completely different despite being completely different Names are identical in almost all respects (Intel® Pentium® Processor G4520 and Intel® Core ™ i3-6100 Processor). The Pentium brand use u. a. the following Intel products:
- 1995: Pentium Pro , workstations and servers
- 1997: Pentium II , successor to the Pentium-1 in the mass market, derived from the Pentium Pro
- 1999: Pentium III , Pentium II with SSE instruction set
- 2000: Pentium 4 , based on the Intel NetBurst microarchitecture, a completely new successor to the Pentium III, supports SSE2 instruction set
- 2003: Pentium M , energy-saving mobile processor , derived from the Pentium III
- 2005: Pentium D , dual-core version of the Pentium 4
- 2007: Pentium Dual-Core , a variant of the Intel Core 2 Duo and thus derived from the Pentium III
- 2010, 2011: Pentium G , a variant of the Intel Core i3 and thus a further development of the Intel Core 2 Duo
- 2013, 2015, 2016: Intel Pentium N / J, energy-saving SoCs with processor cores from the Intel Atom micro- architecture family : Silvermont , Airmont and Goldmont .
- 2018: Intel Pentium Gold, variant from the Intel Coffee Lake microarchitecture
- 2018: Intel Pentium Silver N5000 / J5005, energy-saving SoCs with processor cores based on the Goldmont Plus microarchitecture (Intel code name: Gemini Lake )
- List of microprocessors
- AMD K5
- AMD K6
- Cyrix 5x86
- Cyrix 6x86
- NexGen Nx586
- Rise mP6
- IDT / Centaur WinChip C6
- Pentium (P5): http://datasheets.chipdb.org/Intel/x86/Pentium/24159502.pdf
- Pentium (P54C): http://datasheets.chipdb.org/Intel/x86/Pentium/24199710.PDF
- Pentium MMX (P55C): http://datasheets.chipdb.org/Intel/x86/Pentium%20MMX/24318504.PDF
- Mobile Pentium MMX (P55C): http://datasheets.chipdb.org/Intel/x86/Pentium%20MMX/24329204.PDF
- Mobile Pentium MMX (Tillamook): http://datasheets.chipdb.org/Intel/x86/Pentium%20MMX/24346802.PDF
- Mobile Pentium® Processor with MMX ™ Technology (0.25 Micron Process) Intel SmartDie® Product Specification: http://datasheets.chipdb.org/Intel/x86/Pentium%20MMX/27315402.PDF
- "Famous Names" , The New Yorker , September 26 2011th
- Instruction pairing rules for Intel Pentium Processor. Retrieved June 28, 2020 .
- Anand Lal Shimpi: Chipset Guide. Retrieved June 28, 2020 .
- Intel® Pentium® III Processor 1.13 GHz, 256K cache, 133 MHz FSB ( English ) Intel®. Retrieved May 14, 2019.
- Intel® Pentium® 4 Processor 1.30 GHz, 256K Cache, 400 MHz FSB ( English ) Intel®. Retrieved May 14, 2019.
- Intel® Pentium® Processor G4520 ( English ) Intel®. Retrieved May 14, 2019.
- Intel® Core ™ i3-6100 Processor ( English ) Intel®. Retrieved May 14, 2019.
- N-series Intel® Pentium® Processors and Intel® Celeron® Processors (PDF; 2.3 MB)