Symmetrical multiprocessor system
A symmetric multiprocessing system ( SMP ) is in information technology, a multi-processor - architecture a joint in which two or more identical processors address space possess. This means that every processor with the same (physical) address addresses the same memory cell or the same peripheral register . Most multiprocessor systems today are SMP architectures.
An SMP architecture allows running processes to be distributed dynamically to all available processors - on the other hand, with asymmetrical multiprocessing, each CPU must be assigned a fixed task (e.g. CPU0 executes operating system calls and CPU1 executes user processes), since not all tasks are performed on each Processor can be carried out. However, there are also application domains (e.g. control technology with strict real-time requirements ) in which a static assignment of the processes is also more advantageous on an SMP architecture.
If the hardware is not divided into partitions or CPU sets, an SMP system is also known as a Single System Image (SSI) - only one operating system kernel controls the entire machine.
Symmetrical multiprocessing has been the standard architecture for multiprocessor machines with up to 16 CPUs since the late 1980s.
The requirement that every CPU must be able to execute every process, however, leads to the fact that the memory bus becomes a bottleneck in larger systems . With each additional CPU, the relative gain in performance decreases, since the storage subsystems can no longer deliver the data quickly enough to utilize all available CPUs.
Another problem with SMP is CPU hopping , in which processes constantly switch between the individual CPUs. Normally this would not be a problem, but since CPUs with very large and multi-tiered caches are often used in SMP systems in order to reduce the load on the storage system described above, the rapid change of the running processes also leads to a decrease in performance due to what is known as cache thrashing . This means the constant change of the cache contents through different processes which usually access different data areas. However, you can counteract the effect by assigning a higher affinity of the processes to the respective executing CPU.
With further developments such as NUMA ( Non-Uniform Memory Architecture ), these problems are reduced.
In principle, all modern CPU architectures are more or less suitable for use in SMP systems. There are only differences in the additional hardware required and the expected increase in performance per CPU. While with some CPU variants 2 or 4-fold systems can be built relatively easily, since parts of the required functionality are already implemented in the CPU bus (e.g. all Intel systems with GTL + bus), others Systems require relatively complex point-to-point connections (AMD K7 and DEC / Compaq / HP Alpha with EV6 bus). For reasons of performance, manufacturers are currently switching to integrating the required memory controllers into the CPU. This in turn makes it sensible to integrate several CPU cores on the chip, since a single core cannot always utilize the available data rate of the storage system. Such multi-core processors should not be confused with processors capable of Hyper-Threading , since these are completely independent cores with the associated infrastructure (L1 / L2 caches, FPU, etc.).