Intel Sandy Bridge microarchitecture

from Wikipedia, the free encyclopedia
Sandy Bridge (micro architecture)
Manufacturer Intel
Manufacturing process 32 nm
base Socket 1155
L1 cache 32 + 32 KB per core
L2 cache 256 KB per core
predecessor Nehalem  ( Bloomfield ,    Lynnfield ,  Clarksfield )
Westmere  ( Clarkdale ,    Arrandale ,  Gulftown )
successor Haswell (tock) Broadwell (tick)

The Intel Sandy Bridge microarchitecture is a microarchitecture developed by Intel , on the basis of which the first models were presented in January 2011. "Sandy Bridge" is partly based on the previous architectures "Core" and "Westmere" , with some elements still coming from the Netburst architecture . Intel itself refers to Sandy Bridge processors as “2nd Generation Intel Core Processors” and to Ivy Bridge processors as “3rd Generation Intel Core Processors”.

development

The Sandy Bridge architecture was originally developed under the code name "Gesher" and was first presented at the 2006 Intel Developer Forum . At the IDF 2007 the name was then changed to "Sandy Bridge".

The Sandy Bridge architecture was developed by the same development team that had already released the core architecture (Intel's Israel Development Center , IDC, in Haifa ). Compared to the Nehalem architecture , which comes from a different development team, the pipeline has been shortened again, while the Nehalem architecture has lengthened it from 14 to 16 pipeline stages .

Innovations in the Sandy Bridge architecture

Due to the further integration of components such as the graphics processor (GPU) and the design of the architecture for more than four cores, Intel has built the architecture in a modular manner and abandoned the classic crossbar for connecting the last level cache (L3 cache). Instead, the caches with cores, the memory controller and the GPU are connected to an internal ring bus. This ring bus consists of four links: a 256-bit data ring, a "request ring", an "acknowledge ring" (acknowledge) and a snoop ring (snoop = listening, spying) . The ring bus runs over the cache and does not take up any additional die area. With a processor clocked at 3 GHz, Intel specifies the bandwidth per connection at a theoretical 96 GB / s.

The most comprehensive architectural changes include the successor to SSE4 - instruction set : AVX ( Advanced Vector Extensions , dt .: advanced vector extensions ). While SSE4 calculates on 128-bit wide registers, AVX requires 256-bit wide registers. Thanks to the registers that are twice as wide, up to eight floating point or integer operands can now be combined in a vector and then normal arithmetic or logical operations can be carried out with the vector.

Due to the introduction of 256-bit commands, Intel has reintroduced the "Physical Register File" (PRF) known from the Netburst architecture . While the operands were always carried along with the Core and Nehalem architecture and therefore required additional buffers , which would have had to be further increased with the large 256-bit commands, with the PRF these additional buffers can be dispensed with, since now with a Pointer (pointer variable) on PFR these operands can be reached.

The processing of 256-bit commands is done by interconnecting the floating point with the SIMD integer pipeline, which is achieved using additional transistors, and some functions have been swapped between the pipelines. This procedure saves having to enlarge a pipeline from 128-bit registers to 256-bit registers, but the possible throughput is also lower. In addition, the new implementation does not support fused multiply add (FMA) with 256-bit commands.

The so-called "Dynamic Turbo Mode" has become known as a further innovation. In addition to the functions that are known from the Nehalem / Westmere architecture, the Sandy Bridge processor cores can briefly increase their clock speed beyond the TDP if the processor was previously idle and can therefore be subjected to higher loads for a short time. In the event of continuous load, the processor then regulates itself down to the prescribed TDP.

While the graphics unit in the mobile “Arrandale” offshoot of the Westmere architecture was still overclocked by drivers in special cases, Intel is now integrating the GPU into the hardware-based turbo mode in Sandy Bridge. As with the Nehalem / Westmere architecture, a “Power Control Unit” is built in, i.e. a microcontroller that monitors and controls the energy flows. The cores with the caches, the graphics unit and the integrated north bridge (memory and PCIe controller, DMI) are each connected separately to their own power supply and can be dynamically regulated according to the load.

For some Sandy Bridge models, the “Intel Quick Sync Video” function (hardware-based support for encoding and decoding videos) was available for the first time. "Quick Sync" enables a quick conversion of, for example, a DVD video into a smartphone video format.

Chipset for Sandy Bridge processors

A Cougar Point chipset from the Intel 6 series is required to operate the Sandy Bridge processors . At the end of January 2011, a hardware bug was discovered in this chipset in B2 stepping, which led to a production stop and initially to a recall campaign on the part of Intel. At the same time, the production of the chipset was switched to a bug-free B3 stepping version. Intel later decided to resell the chipsets to OEMs in B2 stepping, as only the four SATA 3 Gb / s ports are affected by the problem and when the two remaining SATA 6 Gb / s ports are used no problems arise. Such mainboards could then be used in notebooks and complete systems in which only two drives are installed in the system. In addition, additional SATA 6 Gb / s ports can be implemented using additional chips.

Ivy Bridge

Ivy Bridge was unveiled on April 23, 2012. Processors based on Ivy Bridge are manufactured in a 22 nm manufacturing process that no longer corresponds to the planar technology that has been common up to now , but uses so-called multigate field effect transistors . However, the Sandy Bridge architecture remains largely the same, at least as far as the processor cores are concerned, because only detailed optimizations are carried out there. The integrated graphics, on the other hand, support DirectX 11, OpenGL 3.1 (OpenGL 4.0 since 9.17.10.2729 beta drivers) and OpenCL for the first time . It is also much more powerful and has its own L3 cache.

The sequel to Ivy Bridge was released in 2013 and is code-named Haswell .

Chipset for Ivy Bridge processors

Ivy Bridge processors are basically compatible with the Intel 6 series chipsets for the Sandy Bridge processors. In addition, with Ivy Bridge, Intel is introducing new Intel 7 series chipsets with additional features such as USB 3.0 interfaces. On many mainboards with chipsets originally developed for Sandy Bridge, processors of the Ivy Bridge generation could be installed after a BIOS update due to the same socket. A processor from the Ivy Bridge series is required to use PCI Express 3.0, since only Ivy Bridge processors have the necessary controller.

Models

Desktop

Sandy Bridge Duo

Dual-core processor

  • L1 cache: 32 + 32 KiB per core (data + instructions)
  • L2 cache: 256 KiB per core with processor clock
  • L3 cache: 3 MiB with processor clock
  • MMX , SSE , SSE2 , SSE3 , SSSE3 , SSE4 .2, Intel 64 , EIST , XD-Bit , IVT , AVX, SMT . Core i5 CPUs also have AES instructions, TXT and VT-d activated.
  • Integrated dual-channel DDR3 memory controller and PCIe 2.0 controller with 16 lanes
  • integrated GPU
  • Socket 1155 , DMI with 5 GT / s ( full duplex , max. 20 Gbit / s per direction) and FDI
  • Power dissipation ( TDP ): 35-65 W.
  • Release DATE: February 20, 2011
  • Manufacturing technology: 32 nm
  • The size: 131 mm² with 504 million transistors including HD-2000-GPU and integr. Northbridge, 149 mm² with 624 million transistors incl. HD 3000 GPU core and integr. Northbridge
  • Clock rates: 2.5–3.3 GHz
  • Models : Intel Core i3-2100 to Intel Core i5-2390T

Sandy Bridge

Quad-core processor

  • L1 cache: 32 + 32 KiB per core (data + instructions)
  • L2 cache: 256 KiB per core with processor clock
  • L3 cache: 6 to 8 MiB with processor clock
  • MMX , SSE , SSE2 , SSE3 , SSSE3 , SSE4 .2, Intel 64 , EIST , XD-Bit , IVT , AES instructions, AVX, TXT . Exception: All processors with a K after the model number and the Core i5 2300 without TXT and Intel VT-d. Also, only the Core i7 CPUs have SMT enabled.
  • Integrated dual-channel DDR3 memory controller and PCIe 2.0 controller with 16 lanes
  • integrated GPU (disabled on some models)
  • Socket 1155 , DMI with 5 GT / s ( full duplex , max. 20 Gbit / s per direction) and FDI
  • Operating voltage ( VCore ): k. A.
  • Power dissipation ( TDP ): 45-95 W.
  • Release DATE: January 9, 2011
  • Manufacturing technology: 32 nm
  • The size: 216 mm² with 1.16 billion transistors (including GPU core and integrated Northbridge)
  • Clock rates: 2.3-3.5 GHz
  • Models : Intel Core i5-2300 to Intel Core i7-2700K

Sandy Bridge E.

Core i7-3930K

Six-core processor (Hexa-Core)

  • L1 cache: 32 + 32 KiB per core (data + instructions)
  • L2 cache: 256 KiB per core with processor clock
  • L3 cache: 12 to 15 MiB with processor clock
  • MMX , SSE , SSE2 , SSE3 , SSSE3 , SSE4 .2, Intel 64 , EIST , XD-Bit , IVT , AES instructions, AVX, TXT , SMT
  • Integrated quad-channel DDR3 memory controller and PCIe 3.0 controller with 40 lanes ( only PCIe 2.0 is officially supported)
  • Socket 2011 , DMI with 5 GT / s ( full duplex , max. 20 Gbit / s per direction)
  • Operating voltage ( VCore ): 0.6-1.35V
  • Power dissipation ( TDP ): 130 W
  • Release DATE: November 14, 2011
  • Manufacturing technology: 32 nm
  • The size: 435 mm² with 2.27 billion transistors (including the deactivated cores)
  • Clock rates: 3.2-3.5 GHz
  • Models : Intel Core i7-3930K to Intel Core i7-3970X

Sandy Bridge E (Quad)

Quad-core processor

  • L1 cache: 32 + 32 KiB per core (data + instructions)
  • L2 cache: 256 KiB per core with processor clock
  • L3 cache: 10 MiB with processor clock
  • MMX , SSE , SSE2 , SSE3 , SSSE3 , SSE4 .2, Intel 64 , EIST , XD-Bit , IVT , AES instructions, AVX, TXT , SMT
  • Integrated quad-channel DDR3 memory controller and PCIe 3.0 controller with 40 lanes ( only PCIe 2.0 is officially supported)
  • Socket 2011 , DMI with 5 GT / s ( full duplex , max. 20 Gbit / s per direction)
  • Operating voltage ( VCore ): 0.6-1.35V
  • Power dissipation ( TDP ): 130 W
  • Release DATE: February 14, 2012
  • Manufacturing technology: 32 nm
  • The size: 294 mm² with 1.27 billion transistors
  • Clock rates: 3.6 GHz
  • Models : Intel Core i7-3820

Ivy Bridge

Quad-core processor

  • L1 cache: 32 + 32 KiB per core (data + instructions)
  • L2 cache: 256 KiB per core with processor clock
  • L3 cache: 6 to 8 MiB with processor clock
  • MMX , SSE , SSE2 , SSE3 , SSSE3 , SSE4 .2, Intel 64 , EIST , XD-Bit , IVT , AES instructions, AVX, TXT . Exception: All processors with a K after the model number and the Core i5-3450 without TXT and Intel VT-d. Also, only the Core i7 CPUs have SMT enabled.
  • Integrated dual-channel DDR3 memory controller and PCIe 3.0 controller with 16 lanes
  • integrated GPU
  • Socket 1155 , DMI with 5 GT / s ( full duplex , max. 20 Gbit / s per direction) and FDI
  • Power dissipation ( TDP ): 45-77 W
  • Release DATE: April 23, 2012
  • Manufacturing technology: 22 nm
  • The size: 160 mm² with 1.4 billion transistors (incl. IGPU and integrated Northbridge)
  • Clock rates: 2.5-3.5 GHz
  • Models : Intel Core i5-3330 to Intel Core i7-3770K

Ivy Bridge Duo

Dual-core processor

  • L1 cache: 32 + 32 KiB per core (data + instructions)
  • L2 cache: 256 KiB per core with processor clock
  • L3 cache: 3 MiB with processor clock
  • MMX , SSE , SSE2 , SSE3 , SSSE3 , SSE4 .2, Intel 64 , EIST , XD-Bit , IVT , AES instructions, AVX, SMT
  • Integrated dual-channel DDR3 memory controller and PCIe 3.0 controller with 16 lanes ( only PCIe 2.0 is officially supported)
  • integrated GPU
  • Socket 1155 , DMI with 5 GT / s ( full duplex , max. 20 Gbit / s per direction) and FDI
  • Power dissipation ( TDP ): 35 - 55 W.
  • Release DATE: September 2, 2012
  • Manufacturing technology: 22 nm
  • The size: 94 mm² (incl. IGPU and integrated Northbridge)
  • Clock rates: 2.8-3.4 GHz
  • Models : Intel Core i3-3220T to Intel Core i3-3240

Mobile

Sandy Bridge

Quad-core processor

  • L1 cache: 32 + 32 KiB per core (data + instructions)
  • L2 cache: 256 KiB per core with processor clock
  • L3 cache: 6 to 8 MiB with processor clock
  • MMX , SSE , SSE2 , SSE3 , SSSE3 , SSE4 .2, Intel 64 , EIST , XD-Bit , IVT , AES instructions, AVX, SMT , TXT . Exception: Core i7-263XQM without TXT , Intel VT-d and AES instructions.
  • Integrated dual-channel DDR3 memory controller and PCIe 2.0 controller with 16 lanes
  • integrated GPU
  • Socket PGA988 (G2) and socket BGA1224, DMI with 5 GT / s ( full duplex , max. 20 Gbit / s per direction) and FDI
  • Operating voltage ( VCore ):
  • Power dissipation ( TDP ): 45-55 W.
  • Release DATE: January 2011
  • Manufacturing technology: 32 nm
  • The size: 216 mm² with 1.16 billion transistors (including GPU core and integrated Northbridge)
  • Clock rates: 2.0–2.7 GHz
  • Models : Intel Core i7-2630QM through i7-2960XM Extreme Edition

Sandy Bridge Duo

Dual-core processor

  • L1 cache: 32 + 32 KiB per core (data + instructions)
  • L2 cache: 256 KiB per core with processor clock
  • L3 cache: 3 MiB to 4 MiB with processor clock
  • MMX , SSE , SSE2 , SSE3 , SSSE3 , SSE4 .2, Intel 64 , EIST , XD-Bit , IVT , AVX, SMT . From Core i5-2500 series, AES instructions, TXT and VT-d are also activated.
  • Integrated dual-channel DDR3 memory controller and PCIe 2.0 controller with 16 lanes
  • integrated GPU
  • Socket PGA988 (G2) and socket BGA1023, DMI with 5 GT / s ( full duplex , max. 20 Gbit / s per direction) and FDI
  • Operating voltage ( VCore ):
  • Power dissipation ( TDP ): 17–35 W
  • Release DATE: March 2011
  • Manufacturing technology: 32 nm
  • The size: 149 mm² with 624 million transistors (including GPU core and integrated Northbridge)
  • Clock rates: 1.4–2.8 GHz
  • Models : Intel Core i3-2310M to Intel Core i7-2677M

Ivy Bridge

Quad-core processor

  • L1 cache: 32 + 32 KiB per core (data + instructions)
  • L2 cache: 256 KiB per core with processor clock
  • L3 cache: 6 to 8 MiB with processor clock
  • MMX , SSE , SSE2 , SSE3 , SSSE3 , SSE4 .2, Intel 64 , EIST , XD-Bit , IVT , AES instructions, AVX, TXT , SMT
  • Integrated dual-channel DDR3 memory controller and PCIe 3.0 controller with 16 lanes
  • integrated GPU
  • Socket PGA988 (G2) and socket BGA1224, DMI with 5 GT / s ( full duplex , max. 20 Gbit / s per direction) and FDI
  • Power dissipation ( TDP ): 35-55 W
  • Release DATE: April 29, 2012
  • Manufacturing technology: 22 nm
  • The size: 160 mm² with 1.4 billion transistors (incl. IGPU and integrated Northbridge)
  • Clock rates: 2.1–3.0 GHz
  • Models : Intel Core i7-3610QM to Intel Core i7-3940XM

Ivy Bridge Duo

Dual-core processor

  • L1 cache: 32 + 32 KiB per core (data + instructions)
  • L2 cache: 256 KiB per core with processor clock
  • L3 cache: 3 MiB to 4 MiB with processor clock
  • MMX , SSE , SSE2 , SSE3 , SSSE3 , SSE4 .2, Intel 64 , EIST , XD-Bit , IVT , AES instructions, AVX, SMT , TXT . TXT is deactivated for models below the Core i5-3320M and for the Core i7-3517U .
  • Integrated dual-channel DDR3 memory controller and PCIe 3.0 controller with 16 lanes, limited to PCIe 2.0 for CPUs with 17 W TDP
  • integrated GPU
  • Socket PGA988 (G2) and socket BGA1023, DMI with 5 GT / s ( full duplex , max. 20 Gbit / s per direction) and FDI
  • Power dissipation ( TDP ): 17–35 W
  • Release DATE: May 31, 2012
  • Manufacturing technology: 22 nm
  • The size: 118 mm² (including iGPU and integrated Northbridge)
  • Clock rates: 1.7–2.9 GHz
  • Models : Intel Core i3-3110M to Intel Core i7-3667U

See also

Web links

Individual evidence

  1. ↑ ark.intel.com
  2. ^ IDF: Roadmap with Penryn, Nehalem, Gesher. In: computerbase.de , September 27, 2006, accessed on May 19, 2010
  3. ↑ IDF: "Gesher" is now called "Sandy Bridge". In: computerbase.de , April 17, 2007, accessed on May 19, 2010
  4. ↑ Intel 6 Series Chipset Specification Update ( Memento from January 25, 2011 in the Internet Archive ) Intel, February 2011
  5. ↑ Is Intel's chipset nightmare coming to an end soon? In: HT4U , February 8, 2011
  6. ↑ Intel HD Graphics Driver v2729 with OpenGL 4 Support and New OpenGL Extensions! In: geeks3d.com , May 6, 2012, accessed May 25, 2012
  7. ↑ Intel's "Ivy Bridge" in the detailed test: Innovations around the iGPU. In: ht4u.net , April 23, 2012, accessed April 23, 2012