Intel NetBurst microarchitecture

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The NetBurst architecture is a microarchitecture newly developed by Intel for the Pentium 4 , which was used in several CPU families.


The architecture relies on a very long pipeline in conjunction with a very simple architecture of the micro-instructions (used internally in the processor for the operations), through which very high clock rates are to be achieved (up to over 4 GHz). Three key technologies are used:

Hyper Pipelined Technology

This is the name for the 20-stage pipeline of the Pentium 4. Compared to the Pentium III with 10 stages, the length of the pipeline has been doubled. This enables significantly higher clock rates. However, the longer pipeline also has disadvantages: The IPC rate has to be lower, and the loss of performance due to an incorrectly predicted jump in the program is considerable, since in this case the content of the entire pipeline has to be disposed of and re-sorted. So Intel tried to make the jump prediction as accurate as possible. The hit rate is around 90%, compared to the Pentium III there are 33% fewer wrongly predicted jumps. The pipeline has expanded over time with the new processor designs and comprised 31 stages in the last design.

Rapid Execution Engine

Since ALUs are present in pairs in the chip, two integer operations can be carried out in one clock cycle by an upstream multiplexer. This partially compensates for the low IPC rate and also improves the integer performance of the CPU.

Execution Trace Cache

The execution trace cache is part of the L1 cache of the CPU. This cache stores decoded microinstructions so that the CPU can dispense with the time-consuming decoding when executing a new instruction. In addition, the micro-instructions are cached in their predicted order of execution.

The End

While the Pentium 4, due to its concept, tended to draw attention to itself with ever new negative records in power consumption, there was a trend reversal with its main competitor, AMD : On the one hand, the Athlon 64 requires a significantly lower processor clock for the same performance, on the other hand it has a dynamic processor clock ( Cool'n'Quiet ), which can reduce power consumption to well below 20 W in many cases.

In addition, the ever higher clock rates of the cores did not bring the same level of performance increase due to the pipeline getting longer with each change of core, and even the inexpensive Celeron series was more expensive to manufacture than the much more expensive Pentium M processors for notebooks. Market.

All this led to Intel abandoning the further development of the Pentium 4 after the Prescott core and stopping work on the Prescott successors Tejas and Jayhawk . The last Pentium 4 core based on NetBurst is the Cedar Mill , which was manufactured in a 65 nm manufacturing process.

The NetBurst architecture (high clock frequencies, long pipelines) thus proved to be a dead end and ultimately led to Intel processors with core micro -architecture . In the notebook ( Core 2 mobile processors) and server market segments ( Xeon family ), too , Intel has removed the entire x86 product range from NetBurst, as Core is characterized by its significantly more efficient work and, at the same time, lower energy consumption. At the same time, the brand name Pentium was pushed into the background. This microarchitecture change is in principle a return to the tried and tested, since the core microarchitecture is a further development of the Pentium M , whose P6 architecture was started in 1995 with the Pentium Pro .

CPUs with NetBurst architecture

See also

Individual evidence

  1. Twenty Years of Intel Pentium Pro: A processor architecture that will last. Retrieved October 31, 2015 .