Intel Core microarchitecture
|Intel Core (microarchitecture)|
|Manufacturing process||65 nm (Intel Core)
45 nm (Penryn)
|base||(µFC-) BGA 956
|L1 cache||32 + 32 KB per core|
|L2 cache||256 KB per core|
The Intel Core microarchitecture is a microarchitecture developed by Intel . It is based on the older Intel P6 architecture and replaced the NetBurst architecture in the desktop and server area. The Intel Core microarchitecture was officially presented on March 7, 2006 at the Intel Developer Forum . The first processors in which they were used were given the name Intel Core 2 . Current processors are based on a further development of this architecture. Since 2008, the architecture has no longer been called Intel Core ( Intel Core Solo / Intel Core Duo ) or Intel Core 2, but has been renamed Intel Core i . The Intel Nehalem microarchitecture represents the first generation of these processors called Intel Core i.
The processors most closely related to the Intel Core microarchitecture belong to the Intel Pentium M and Intel Core series , which are based on a modified variant of the P6 architecture . The core micro-architecture was developed on the basis of these mobile processors in Intel's Israel Development Center (IDC) in Haifa . A central feature, which was added from the NetBurst architecture , is the 64-bit expansion Intel 64 .
The Intel Core microarchitecture with its relatively short, 14-stage pipeline, in contrast to the max. 31 levels of the Netburst architecture designed for rather moderate clock rates and achieves its performance mainly due to a high number of commands per clock cycle ( IPC = Instructions per cycle ). Therefore, processors with the same performance have a significantly lower power consumption compared to the NetBurst architecture, whereas the thermal design power had to be increased compared to the Intel Core . Most of the products have multiple cores, but there are also single-core processors sold as Celeron or Core 2 Solo .
The Intel Core microarchitecture uses a quadruple superscalar design, while all predecessors (Intel Pentium M / Intel Core or NetBurst processors) are based on a triple superscalar design. Intel calls this extension "Intel Wide Dynamic Execution". The bus of the SSE units has also been widened . The design of the predecessor only offered 64 bits, while the new architecture enables 128 bits. Therefore, SSE, SSE2, and SSE3 instructions can be processed in just one clock cycle. In addition, new SSSE3 commands have been integrated. Intel describes this feature as "Advanced Digital Media Boost".
The ability, taken over from the IA-64 and Netburst architecture , not only to speculatively load data into the cache in advance ( prefetching ), but also to process it ( memory disambiguation ), is called "Smart Memory Access" by Intel. If the speculative execution turns out to be wrong, the result is discarded and a new start is made. The L2 cache can be dynamically assigned to the various CPU cores ("Intel Advanced Smart Cache"). If one CPU core is inactive, the entire L2 cache is assigned to the other CPU core.
A new power-saving concept has been integrated under the name "Intel Intelligent Power Capability", which, compared to SpeedStep, has a finer gradation and therefore works more efficiently.
With the shrink from 65 nm to 45 nm, which happened at the end of 2007 under the code name "Penryn", SSE4.1 was introduced. The “Super Shuffle Engine” was also introduced for SSE commands, which is intended to accelerate activities to be carried out before and after the calculation. The division unit was equipped with the Radix-16 divider instead of the previous Radix-4 divider . In concrete terms, this benefits commands that have to perform division or root calculations. The "Memory Order Buffer" has been optimized. It can now better manage addresses that have not been aligned , since store forwarding can now also be used more frequently on these. This minimizes load latencies , waiting for a cache update and access to the cache is not necessary in such cases. The Intel Virtualization Technology has also been improved in detail, and other small optimizations have been made to the architecture.
In the case of processors for notebooks, the power management has been extended to include deep power down mode (C6), in which all executing units of the processor and the caches are completely switched off. Since C6 is not always worthwhile, an algorithm is used to decide whether the command to C6 coming from the operating system is to be executed or whether it is ignored and only switched to C4 instead.
CPUs with Intel Core microarchitecture
- Intel Celeron (Core)
- Intel Celeron M : from "Merom-1024"
- Intel Core 2
- Intel Pentium Dual-Core : from "Allendale-1024" or "Merom-1024"
- Intel Xeon (Core)
Processors named Intel Core are not based on the Intel Core microarchitecture.