Supplemental Streaming SIMD Extensions 3
SSSE3 ( S upplemental S treaming S IMD E xtensions 3 ) indicates the with Intel's Core architecture introduced enhancements to the SSE3 -Befehlssatzes. The terms Tejas New Instructions (TNI) or Merom New Instructions (MNI) are also used within the company. SSSE3 is often incorrectly referred to as SSE4 , but SSE4 is a completely different instruction set extension.
New orders
SSSE3 extends the SSE3 instruction set by 16 new instructions. Since these can be applied to both 64-bit MMX registers and 128-bit SSE registers, Intel states that there are 32 commands.
- psignw, psignd, psignb
- pshufb
- pmulhrsw, pmaddubsw
- phsubw, phsubsw, phsubd
- phaddw, phaddsw, phaddd
- palignr
- pabsw, pabsd, pabsb
SSSE3 was presented as part of the Intel Core microarchitecture and was integrated for the first time in the processor cores Merom ( notebook ), Allendale / Conroe ( desktop ) and Woodcrest ( server ).
CPUs with SSSE3
- Intel Atom (all processors)
- Intel Celeron (from processor core Conroe-L )
- Intel Celeron M (from processor core Merom-1024 )
- all processors of the Intel Core 2 series
- all processors of the Intel Core i series
- Intel Pentium Dual-Core
- Intel Xeon (from processor core Woodcrest )
- VIA Nano
- AMD bulldozer
- AMD Fusion
- AMD Ryzen
Footnotes
- ↑ Intel Function Reference NZ ( Memento of the original from April 28, 2011 in the Internet Archive ) Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice.
