IA-32


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As IA-32 , an abbreviation for " Intel Architecture 32-Bit ," Intel describes the architecture of the x86 processor from the 80386 , originally as 32-bit architecture . With the instruction set extension x64 , however, the 64-bit x86 architecture is also included.

x86 is the general name for the processor architecture , which was established with the 8086 processor from Intel in 1978 as a 16-bit architecture . With the 80386 , Intel introduced an expansion of the instruction set to 32-bit in 1985 , which is why the designation i386 or retronym IA-32 is often used for 80386-compatible microprocessors . From 1999 onwards, AMD was working on expanding the instruction set to 64-bit, initially under the name x86-64 , which was introduced in 2003 as AMD64 and in 2005 by Intel as Intel 64 . This extension of the instruction set, now often referred to as x64 , is also part of the " Intel Architecture 32-bit ."

The x86 instruction set architecture is being further developed by Intel and AMD.

Itanium

With the new development of the Itanium processor by Intel and Hewlett-Packard , which came onto the market in 2001, Intel wanted to introduce the Itanium architecture , which was incompatible with x86 and IA-32 . This was also called " Intel Architecture 64-Bit " by Intel , because Intel saw the new architecture as the successor to the then 32-bit x86 architecture. IA-64 (Itanium) did not catch on, however, also because the architecture as a new development is not x86-compatible and therefore does not belong to the IA-32 architecture with i386 instruction set, which was implemented by many manufacturers .

Since x86 had been the most widespread processor architecture for personal computers worldwide since the 1980s , there were a large number of existing programs that had to be reprogrammed for the Itanium processor - or: should have been programmed.

When AMD introduced the 64-bit extension AMD64 for the existing x86 architecture (IA-32) in 2003 , it was immediately accepted by the market, partly because existing x86 programs ran unchanged on it. In 2005, Intel had to follow suit and implemented with Intel 64 a 64-bit extension for the x86 architecture "IA-32" that is compatible with AMD64, which makes the " Intel Architecture 32-bit " a 64-bit architecture. To avoid confusion, 64-bit x86 is also referred to as x64 (based on x86 ).

IA-64, however, stands for the Itanium architecture, which is also a 64-bit architecture, but which is not compatible with the x86 instruction set "IA-32" ( 80x86 , i386 , x64 ).

Architectural features

The IA-32 architecture is a further development of the 16-bit architectures of Intel's 8086 and 80286 processors. All registers , including the address registers, were expanded to 32 bits in this architecture , the number of registers remained the same. The 32-bit registers were implemented as an extension of the 16-bit registers of the 80286 architecture in order to achieve downward compatibility. The mnemonic of the extended registers were marked with a preceding E , for extended (German: extended) (to e.g. EAX (32-bit register) from previously AX (16-bit register)). Under the designation for the 16-bit register of the 80286 architecture, the lower 16-bit of the 32-bit register can still be accessed (e.g. with AX access to the lower 16-bit of the 32-bit EAX register).

The address bus is 32 bits wide and therefore addressability is limited to 4  GB (physical address space). Exceptions are the 80386SX , which only had a 24-bit address bus. Starting with the Pentium Pro , an address extension to 36 bits was achieved using PAE ; later generations even more, e.g. B. 40 bits on the AMD K8 . With 36 bits, 64 GiB can be addressed, so that more than 4 GiB can be used in a 32-bit environment with restrictions if the PAE is implemented by the operating system. For example, Linux uses the PAE extension automatically if it is supported by the processor - PAE is even a prerequisite for newer distributions, since it can also use the NX bit . Under Windows from Microsoft, however, PAE is not used due to compatibility problems with existing drivers, so that 32-bit versions of Windows are limited to 4 GiB of RAM.

With the 64-bit instruction set extension x64 , IA-32 was further developed to a 64-bit architecture, whereby the number of registers was also doubled. In the new operating mode, both 32-bit and 64-bit sub-modes are available, so that 32-bit software can also benefit from twice the number of registers ( x32 ).

Operating modes

In addition to the real mode , in which the conventional main memory and the upper memory area , that is the first, lower megabyte of the main memory, can be addressed without restriction via offset and segment , compatible with the 16-bit Intel-8086 , the Intel Architecture 32- Bit two or three further operating modes:

  • Protected mode , which can continuously (linearly) address up to 4 GB of memory and guarantees hardware-side memory protection (via the virtual memory management of the MMU ), which enables multitasking / multiuser operating systems with preemptive multitasking .
  • System Management Mode (SMM), which is used for power reduction and manufacturer-specific properties. The SMM runs in a separate main memory so that running processes and operating systems are not influenced.
  • In the case of 64-bit x86 processors, the IA32e mode (Intel) or the long mode (AMD), which provides the two sub-modes 64-bit mode and compatibility mode, are also available. (See x64 # operating modes .)

As an option of Protected Mode (32-bit) there is also the Virtual 8086 Mode , which can execute one or more real-mode programs - this was required and was important for the execution of MS-DOS -compatible programs under 32-bit operating systems for a gentle migration from DOS to more modern operating systems. Since the changeover to 64-bit, the Virtual 8086 mode no longer plays a very important role, as MS-DOS-compatible programs are only used relatively little or they (have to) be fully emulated on 64-bit operating systems.

Protected Mode: Virtual memory management and memory protection

Virtual memory management

The new virtual memory management is primarily designed for multitasking operation ( protected mode ). Using the Memory Management Unit (MMU), several programs in the memory can be executed quasi-simultaneously without conflict. For this purpose, each program is executed in a (virtual) memory space in which it exists on its own and therefore cannot have memory access conflicts with other programs, so that memory protection is achieved (e.g. "Program A mistakenly overwrites a variable in the memory in program B" can no longer occur). The MMU achieves this via a table ( TLB ) in which the real physical address of a memory block is noted for the last localized virtual address of all programs. With every access (requesting memory, writing or reading), transparently for programs and programmers, a clear physical address is diverted. Another positive effect is that memory fragmentation of the physical memory can no longer occur. The address translation enables the MMU to present the program with almost any fragmented physical memory as a continuously accessible block of virtual memory. This is an effective mechanism as long as the size of the physical memory is significantly smaller than that of the virtual address space (4 GB). Due to the continuously falling RAM memory prices, this is no longer the case; the virtual memory space can no longer always conceal the fragmentation of the physical memory, since it can now itself be too fragmented.

IA-32 address translation

Virtual address translation

The IA-32 architecture uses a 48 bit wide segmented logical address, which consists of 16 bits of selector and 32 bits of offset. The segmentation translates the logical address into a linear 32-bit address and can then be translated into a physical 32-bit address using the paging mechanism . If the system does not use paging, the 32-bit linear address is the physical address.

Protection functions through the virtual memory management

The MMU contains four central system registers GDTR ( Global Descriptor Table Register ), IDTR ( Interrupt Descriptor Table Register ), LDTR ( Local Descriptor Table Register ) and TR ( Task Register ). The protective mechanisms are thus implemented.

The IA-32 architecture contains the following five protective functions for multitasking / multiuser operation:

  1. Type check
  2. Limit check
  3. Access to data
  4. Control transfer
  5. Instruction check

These protective functions are implemented with various hardware mechanisms.

More functions

Further functions have been added in the following CPU generations:

  • The models of the i486DX have already integrated a math coprocessor , and a cache has also been integrated on the chip (the budget version i486 SX was manufactured with a deactivated coprocessor). In addition, the execution unit was built on the assembly line principle , called the processor pipeline , which significantly increases the throughput of instructions.
  • With the Pentium , a second execution unit was added to the architecture. These now parallel execution units, called pipelines U and V , enable superscalar program execution via out-of-order execution of the processor.
  • In the Pentium MMX , commands have been added that process multiple integer data at the same time ( SIMD ) - this is particularly useful for multimedia data. MMX stands for Matrix Math Extensions” , but also often called Multi Media Extensions” by marketing .
  • With the Pentium III, the SIMD commands have been expanded so that floating point numbers can also be processed ( Streaming SIMD Extensions / SSE ).
  • Starting with the Prescott models of the Xeon / Pentium 4 series, the processors have been expanded to include a 64-bit mode ( Intel 64 , formerly also called EM64T), which is largely similar to the AMD64 mode of the Opteron and Athlon 64 -Competitive AMD CPUs .

See also

Web links