Itanium is a 64-bit architecture with EPIC - instruction set jointly by Hewlett-Packard and Intel for the same Itanium processor ( code name was developed Merced). At the end of the 1990s, the instruction set architecture, also known as the English Intel Architecture 64 ‑ bit , or IA-64 for short , was introduced because it should have completely replaced the then 32 ‑ bit x86 architecture IA ‑ 32 . IA ‑ 32 (x86) is a CISC architecture - the more modern architecture of the Itanium, IA ‑ 64, with the VLIW EPIC paradigm was expected to accelerate execution. The Itanium architecture differs significantly from the x86 architecture, which initially only kept existing x86 software executable via a slow emulation . In order to really benefit from the new architecture, operating systems and programs for IA-64 had to be rewritten.
The Itanium architecture (IA-64) was placed exclusively on the server market by Intel . Operating systems such as Windows XP from Microsoft were also ported to IA ‑ 64, but after 2005 only the server operating system line remained - after 2010, however, this will no longer be further developed as Windows Server 2008 R2 (October 2009) is the last Itanium for the time being Version stayed.
Intel wanted to establish IA-64 as the successor to the then 32-bit x86 architecture - called "IA-32" by Intel. Together with HP, Intel first tried to gain a foothold in the 64-bit server market, which has been consistently 64-bit since the early 1990s. In the desktop area, Intel initially stopped at 32 ‑ bit with x86 alias IA-32.
However, IA-64 aka Itanium was not at all compatible with x86, for which there was already a large amount of established software. Ultimately, it was the x86 competitor AMD who, with the 64 ‑ bit expansion AMD64, which was developed in 1999 and introduced in 2003, made the x86 instruction set IA ‑ 32 also a 64 ‑ bit architecture. The x86 architecture "IA-32" remained - in contrast to the Itanium architecture "IA-64" - compatible with existing software. Since the Pentium Pro , x86 processors have also been using RISC - Opcode (μOps) internally , so that this advantage was no longer given with the Itanium architecture. Traditionally, AMD and Intel have x86-specific license agreements that allow each other to use the new features introduced in the instruction set. In order not to lose the x86 market, Intel followed suit in 2005 with the x86 instruction set extension Intel 64 (previously also called IA ‑ 32e and EM64T), which is largely compatible with AMD64 . With the Opteron processors with AMD64 (64-bit x86) introduced in 2003, AMD was able to provide inexpensive and at the same time 64-bit capable servers on the server market and was very successful with it. Intel itself was in direct competition with IA-64 (Itanium) in the same way with its own 64-bit x86 server processors.
Since IA-32 (x86 architecture) and IA-64 (Itanium architecture) do not offer a clear separation between 32- and 64-bit, 64-bit x86 processors are designated with x64 (based on x86) for a clearer distinction - these are now much more widespread than the Itanium architecture.
The design is based on a concept called Explicitly Parallel Instruction Computing (EPIC), which is similar to the traditional Very Long Instruction Word (VLIW), but with a number of improvements. With EPIC, the processor commands, which are not dependent on one another and can therefore be executed in parallel, are divided into instruction groups using predefined patterns and passed on to the processor, which can then decide, based on its own capabilities, how many of the theoretically possible instruction groups are actually executed in parallel become. The idea behind this is that the compiler or even the assembler determines how much parallelism is possible taking dependencies into account and records this accordingly in the program code, and the processor can later optimally utilize the pipelines , depending on how many instructions it actually has can run in parallel.
The architecture tries to reduce memory latency by having a large number of registers on the processor. There are 128 64-bit registers for integer calculations, 128 82-bit registers specially for floating point data and 64 1-bit forecast registers via which the commands are conditionally executed. This allows more information to be kept in the registers instead of having to go the slow route via cache or memory every time data is needed. Due to the conditional executability of almost all instructions, there is a drastic reduction in conditional jump instructions.
To run 32-bit software, the processor uses part of the IA-64 registers as IA-32 registers. In addition, there is a jump command in the IA-32 that is used to switch to the IA-64 mode (back). If this is used on an IA-32 processor, an invalid opcode interrupt occurs there.
The architecture has a large instruction set, some of which are very complex. Among other things, there are special processor commands for multimedia and complex floating point operations.
In the software, when a function is called, the current register contents are written to the stack and retrieved after the function has expired. This causes waiting times and slows down the program flow. The IA-64 design reduces this latency by performing these stack operations on the registers themselves. The so-called Register Stack Engine (RSE) handles the cases in which the registers and the memory have to be synchronized.
Although the independence of the IA-64 architecture was emphasized right from the start, they wanted to adorn themselves with the rating IA-32 compatible. Older Itanium variants therefore also support IA-32 commands on the hardware side at the Pentium III level . Since it is only an emulation unit , the performance of 32-bit software on an IA-64 system does not come close to the performance of the same software on a comparable x86 system. In addition, Itanium processors are only compatible with IA-32 to a limited extent, since, for example, paging runs via the IA-64 architecture and an attempt to load the CR3 (Page Directory Base Register) with a value is intercepted by this. A software-based variant of the x86 emulation called IA-32 EL has been used since Itanium 2 . Thanks to various optimizations, this is faster than the hardware-based variant, but still slower than a comparable clocked x86 processor. In general, however, the ability to emulate IA-32 has largely lost its importance, and all software packages that are important for the target market are now also available in a native IA-64 version. In addition to the IA-32 software emulator, there is also the HP-UX ARIES (Automatic Re-translation and Integrated Environment Simulation) package to emulate the PA-RISC architecture .
Progress or backward compatibility
The IA-32 architecture is backwards compatible up to the architecture of the Intel 8086 processor from 1978. This means that legacies from previous architectures have to be carried over into new designs. As a result, on the one hand, modern design approaches cannot be implemented in the best possible way; on the other hand, it is not possible to create a coherent architecture (for example with regard to uniform operation code formats). The advantage of downward compatibility is that the existing software can still be used without any problems ( porting ) and recompilation .
Intel tried to clean up the legacy issues (also to set itself apart from its competitor AMD, which mainly owned x86 patents and competencies) and published the IA-64 architecture, an independent architecture that is not an extension of the existing IA-32. The instruction set. The price to be paid for this is that software written for the IA-32 instruction set can only be executed to a limited extent on the new architecture. Even the code that can still be executed is partially emulated on a software basis , which leads to poor software performance .
This daring step by Intel proved to be unenforceable on the free market, also because IA-32 processors were still mainly manufactured for the end-user market and the IA-32 compatibility mode in the Itanium was extremely slow. The necessary adaptation to use the Itanium capabilities for the enormous amount of existing software would have been very time-consuming, even in an optimistic, problem-free case, a recompilation and delivery of the software would still be necessary. In the worst case, time-consuming bug fixes, adjustments or the complete rebuilding of software would be necessary, e.g. B. because the source code for software is not always available, for example in the event that a manufacturer has since gone bankrupt. Another problem was an initially moderate performance even of specifically adapted Itanium software, as both software developers and compiler manufacturers first had to gain experience with the new Itanium architecture in order to be able to optimally support it, a knowledge that has been for the x86 architecture for many years was built.
Compared to the IA-32 / AMD64, the " instruction set efficiency " is much worse due to longer instructions and difficult to avoid NOP filling instructions , which means that the IA-64 architecture shows poorer results in many benchmarks.
Itanium processors are available under the following names:
- Intel Itanium (2001-2002)
Intel Itanium 2 (from 2002)
- HP Itanium 2
Operating systems available for the Itanium architecture (IA-64) have been and still are. a .:
- FreeBSD , only as Developmental Architecture ( Tier 2) from Version 5 to Version 10
- NetBSD , just unfinished and very experimental
- Windows (further development discontinued)
- Description from the manufacturer Intel (English)
- ↑ Jürgen Kuri: Microsoft is discontinuing Windows XP for the 64-bit Itanium CPU. In: Heise online . January 6, 2005 . Retrieved February 25, 2017.
- ↑ a b Christof Windeck: Microsoft no longer programs new Itanium software. In: Heise online . April 6, 2010 . Retrieved February 25, 2017.
- ↑ Michael Kanellos: AMD rolls dice on Opteron chip ( English ) CNET News. April 21, 2003. Retrieved May 10, 2012.
- ^ Andy Patrizio: Why Intel can't seem to retire the x86. ITworld, March 4, 2013, accessed April 15, 2013 .
- ^ Support for Multiple Architectures. 18.3. Tier 2: Developmental Architectures. In: Committer's Guide. The FreeBSD Documentation Project, accessed March 5, 2017 .
- ↑ FreeBSD / ia64 5.0-DP2 Hardware Notes. The FreeBSD Documentation Project, November 7, 2002, accessed March 5, 2017 .
- ↑ FreeBSD / ia64 Project. The FreeBSD Project, accessed on March 5, 2017 (English): "The ia64 port is considered a tier 2 platform through FreeBSD 10. After this it will no longer be supported."
- ↑ NetBSD / ia64. In: NetBSD Wiki / ports /. The NetBSD Foundation, Inc., accessed March 5, 2017 .