PA-RISC

Processor core (die) photo of an HP PA-7000 (PCX-S)

Processor core (die) photo of an HP PA-7100LC (PCX-L)

Parallel / Precision Architecture Reduced Instruction Set Computer ( PA-RISC ) is a microprocessor architecture from Hewlett-Packard for use in servers and workstations . As is evident from the name, is a processor of RISC type transmission, the PA is short for Precision Architecture . It is also known under the name HP / PA for H ewlett P ackard P recision A rchitecture . The first processors were used in 1986, and production was finally discontinued in 2008. A few years earlier, HP began to use the Itanium or Itanium 2 processors developed together with Intel instead .

history

In the late 1980s, HP produced four lines of computers, each using different CISC processors. The PC-compatible HP Vectra series, introduced in 1986, was based on Intel 80286 processors. All other model series used CPUs from other manufacturers. The HP 200 series (1981) and HP 9000 300 series (1985) Unix ( HP-UX ) workstations were based on the Motorola 68k design. An additional 68k-based series was added in 1989 through the acquisition of Apollo , the later HP Apollo 9000 series 400 . The next independent series was the HP 300 series (1978), integrated multi-user computers based on a proprietary Silicon-on-Sapphire CPU design 8 (SoS design) and the Amigo / 300 operating system. The first series of the Hewlett-Packard 3000 series (1972) were also based on a SoS design and the MPE (operating system) . Finally, there was the HP 9000 Series 500 (1982) - minicomputers which the self-developed by HP 32- bit - FOCUS - CPU used. All non-Intel-based HP systems were consolidated into a uniform design from 1988 with the help of the new PA-RISC processor.

The first series of PA-RISC-7000 processors were designed for an address space of 32 bits and were initially used from March 1986 in the HP-3000 series for the models 930 and 950 and in the HP-9000 840s, which is identical to the 930.

A feature of the PA-RISC range is that most generations of these CPUs do not have a level 2 cache . Instead, large level 1 caches are used, initially connected as separate chips via a bus , and later integrated on a chip. Only the PA-7100LC, PA-7200 and PA-7300LC had an L2 cache. Another innovation in the PA-RISC design were the additional so-called multimedia instructions ( SIMD ), which were introduced for the first time with the PA-7100LC. As of the PA-7200, the external MMC / SMC memory controller was also used; for the first time, it enables a 36-bit address space (with the K420 max. 8 GB, otherwise max. 32 GB main memory) on which the 32-bit versions can also use from HP-UX version 11.00 or higher via “ Memory Windows ” (compare PAE or AWE ).

In 1994 the PA-RISC-2.0 specification , which is still valid today, was defined, which provides a word length of 64 bits and thus enables a linear address space that is larger than 4 GB. Further changes concerned the pipeline architecture and the division of the instruction cache into two units, one for instructions that are processed quickly, one for those that are more time-consuming. The first representative of the new standard was the PA-8000.

Production of the PA-RISC processors was originally supposed to end in 2004, but was expanded due to various delays in Itanium development. The production of new systems based on the HP-PA processor architecture ended on December 31, 2008. The IA-64 architecture (Itanium) developed by HP together with Intel since the late 1990s is used as the successor .

The PA-RISC processors are supported by NetBSD , OpenBSD or Linux , among others . Since the release of Debian 3.0 (Woody), HPPA is an officially supported Debian architecture, the current stable distribution of Debian-HPPA GNU / Linux is version 6.0. It was released on February 6, 2011. Also Gentoo Linux supports HPPA. An Ubuntu port also existed up to release 9.04 (“Jaunty”). Since release 9.10 there is no further Ubuntu support for PA-RISC processors. In general, the HPPA ports have become quiet.

Model history

image	model	Type	year	Frequency in MHz	Memory bus in MB / s	Production in µm	Transistors in millions	The size in mm²	Consumption in W	Dcache in kbit	Icache in kbit	L2 cache in MB	ISA
	TS-1	PA-1.0	1986	8th	?	TTL	6 × 150 ICs	6 ″ × 8.4 ″ × 11.3 ″				-	1.0
	CS-1	PA-1.0	1987	8th	?	1.6	0.164	72.93				-	1.0
	NS-1	PA-1.0	1987	25-30	?	1.5	0.144	70.56				-	1.0
	NS-2	PA-1.0	1989	27.5-30	?	1.5	0.183	196	27			-	1.0
	PCX-S	PA-7000	1991	35-66	?	1.0	0.58	201.6	?	256	256	-	1.1a
	PCX-T	PA-7100	1992	33-100	?	0.8	0.85	196	?	2048	1024	-	1.1b
	PCX-T	PA-7150	1994	125	?	0.8	0.85	196	?	2048	1024	-	1.1b
	PCX-T '	PA-7200	1994	120	960	0.55	1.26	210	30th	1024	2048	-	1.1c
	PCX-L	PA-7100LC	1994	60-100	?	0.75	0.9	201.6	7-11	-	1	2	1.1d
	PCX-L2	PA-7300LC	1996	132-180	?	0.5	9.2	260.1	?	64	64	0-8	1.1e
	PCX-U	PA-8000	1996	160-180	960	0.5	3.8 / 4.5?	338/347?	?	1024	1024	-	2.0
	PCX-U +	PA-8200	1997	200-240	960	0.5	3.8 / 4.5?	338/347?	?	2048	2048	-	2.0
	PCX-W	PA-8500	1998	300-440	1920	0.25	140	467	?	1024	512	-	2.0
	PCX-W +	PA-8600	2000	480-552	1920	0.25	140	467	?	1024	512	-	2.0
	PCX-W2	PA-8700 (+)	2001	625-875	1920	0.18	186	304	?	1536	768	-	2.0
	Mako	PA-8800	2003	900-1000	6400	0.13	300	361	?	768 / core	768 / core	32	2.0
	Shortfin	PA-8900	2005	1000-1100	6400	0.13	?	?	?	768 / core	768 / core	64	2.0

Web links

• Specifications PA-RISC 2.0
• The OpenPA project engl. With a lot of information and images of various PA-RISC based systems. (Also non HP) With a section about free operating systems on PA-RISC HP9000 machines.

Individual evidence

1. ↑ http://hpmuseum.net/display_item.php?hw=836
2. ↑ http://www.netbsd.org/ports/hp700/
3. ↑ http://www.openbsd.org/hppa.html
4. ↑ http://parisc-linux.org
5. ↑ http://www.debian.org/ports/hppa/
6. ↑ Debian 6.0 "Squeeze" released. In: debian.org. Software in the Public Interest, Inc., February 6, 2011, accessed February 8, 2011 . 
7. ↑ http://www.gentoo.org/doc/en/handbook/handbook-hppa.xml