Instruction set architecture
An instruction set architecture ( English Instruction Set Architecture , short: ISA) is the abstract description of the behavior of a computer in relation to its instruction set . The instruction set architecture is formulated in such a way that it is independent of a specific implementation. The ISA is also part of processor architectures such as B. x86 , ARM or PowerPC and usually bears their names (e.g. x86 instruction set ).
An instruction set architecture is specified by a formal description. They are mainly a assembly language - programmers the opportunity uniform conduct of machine code for different implementations of a particular ISA ( micro-architectures or virtual machines ) with respect to register , data types to understand etc. This enables him or her to create binary compatible programs for different processors if they use the same instruction set architecture.
The formal specification of an instruction set architecture includes the description of the instruction set and its binary coding as well as a description of the behavior of the CPU during certain operating states and when certain events occur: In this context, for example, the behavior of the CPU in the event of an interrupt request , the start address of the Command processing and the initialization of the registers after a reset , but also the construction of important data structures (e.g. the various descriptor tables in the protected mode of the x86 processors ). This list does not claim to be complete and is only intended to make it clear that the specification of an instruction set architecture is more than the description of the individual commands in its instruction set.
Forms of implementation
It is said that a microprocessor implements or supports an instruction set architecture if it can execute all programs that are valid within the meaning of the rules of this instruction set architecture in the intended manner. However, many instruction set architectures that actually exist have grown historically and have never been formally specified. This is often not even desired, since an exact specification would possibly enable a competitor to build CPUs with this instruction set architecture himself and relieve him of the task of finding out for himself which properties of a vaguely described instruction set architecture are the ones that are, for example, allow backward compatibility to a historically grown stock of software to be maintained. The history of x86-compatible CPUs shows this very impressively: In the first half of the 1990s, the new developments from Intel competitors in particular repeatedly showed more or less significant incompatibilities with the Intel model. In practice, some properties that are not documented in the data sheets or seemingly insignificant details of a specific CPU often become part of an instruction set architecture.
Since an instruction set architecture is only a formal definition, it does not have to be implemented as a processor or even exclusively . It can also be implemented in software as a so-called virtual machine . One then speaks of an emulation . In this way, software for an instruction set architecture can also be executed and tested before the associated CPU has even been built. Thus, large parts of the IA-64 Support for the operating system kernel Linux programmed before the first Itanium Intel's factories left. This is also the reason why Linux was able to run on the Itanium CPU shortly after the first test samples were available.
Instruction set architectures are classified based on the following characteristic properties, among others:
- Type of instruction set
- Bit width
- Number of registers
- Addressing types
- Interrupt requests and exception handling
A few of these aspects are briefly discussed in more detail below, mostly referring to further articles.
Type of instruction set
- CISC - "Complex Instruction Set Computing"
- RISC - "Reduced Instruction Set Computing"
- VLIW - "Very Long Instruction Word"
- EPIC - "Explicitly Parallel Instruction Computing"
Further characteristic properties of instruction sets can be found in the instruction set article .
The bit width of an instruction set architecture is expressed in the bit width of the data and address registers visible to the programmer and that of the processing units. In most cases, the width of the data register is considered to be decisive for the bit width of the instruction set architecture.
Examples for the bit widths of the instruction set architectures of different CPUs and CPU families are:
- 8 bit
- 16 bit
- x86-compatible processors from the 3rd generation - this instruction set architecture is also known as IA-32
- 68k family - the first generation of CPUs in this family with the designations 68000, 68008, 68010 and 68012 are based on a 16-bit microarchitecture , although their instruction set architecture was 32- bit from the start.
- 64 bit
Type and number of registers
The number of available or implementable registers is an important criterion when assessing an instruction set architecture. Just like the various types of addressing, it also flows directly into the binary coding of an instruction set. The following article explains more about the different types of registers: Register (Computer)
The number of registers is not always precisely specified by the instruction set architecture. So it is quite conceivable that the binary coding of the instruction set provides a maximum number of registers, but for concrete implementations it can allow a smaller number of registers. In this way, one and the same instruction set architecture can be adapted or optimized for different purposes. The same applies to optionally implementable commands. This approach is particularly popular with microcontroller families, as on the one hand it allows a development or configuration of the CPU core that is optimized for the intended use of a CPU or a microcontroller, but on the other hand it ensures that development tools and documentation do not have to be constantly fundamentally modified. In addition, the developers do not have to be retrained or retrained.
Number of operands
A fundamental characteristic of a CPU is the maximum number of operands that a single instruction can accept. Only operands that are loaded from the main memory are counted, but not operands that have already been loaded into internal processor registers. When naming the associated architectures, one speaks of addresses instead of operands . One differentiates:
- One-address architecture: An instruction fetches a maximum of one operand from the main memory. If more operands are required, for example for an addition or a comparison, they must have been loaded into internal processor registers (usually the accumulator ) beforehand . The one-address architecture is the predominant one today. There is a more extensive specification for the RISC processors, namely that there is only access to memory addresses for pure load and save commands, all more complicated links take place exclusively within the register set.
- Two-address architecture: An instruction fetches a maximum of two operands from the main memory, for example the summands of an addition. There is then a distinction in the architectures as to whether the result is stored in an internal processor register by default (and is available there for further processing and queries), or whether the result is directly returned to one of the two operand addresses (for example the first of the two ) is restored. The latter method was used with CPUs that did not have internal registers. In general, this architecture is rarely used today.
- Three-address architecture: An instruction fetches a maximum of three operands from the main memory, typically the two operands of an arithmetic or logical combination and, as the third operand, the address to which the result is to be saved. This architecture was used very rarely.
Assembly language and mnemonics
In connection with the specification of an instruction set architecture, the need to define an assembly language is often mentioned , which assigns its instructions, among other things, so-called mnemonics and defines the format of the associated operands . When assessing different CPUs with the same instruction set architecture, however, this aspect does not play a role. Manufacturers can implement CPUs with the same instruction set architecture, although their data sheets contain different symbolic representations for their instructions. For example, Intel has fundamentally changed the mnemonic representation of its assembly language for the 8008 in its data book from 1975 compared to the data book of the previous year. Even so, the 8008s made in 1974 and 1975 undoubtedly implement the same instruction set architecture. When comparing the instruction set architectures of two CPUs, this aspect cannot therefore be used as a comparative criterion.
In addition, there are other properties of instruction set architectures that should only be mentioned briefly here.
- is multitasking supported?
- is there a stack ?
- how is it organized?
- what can it be used for?
- are there commands for floating point arithmetic?
Aspects not belonging to the instruction set architecture
- the micro- architecture, i.e. the internal structure of the processor.
- everything that does not affect the core of the CPU, e.g. peripheral devices , DMA and interrupt controllers, bus systems and main memories
The IBM S / 360 instruction set architecture
The first instruction set architecture that has been repeatedly reimplemented and continuously expanded at different speeds, levels of complexity and technologies is that of the IBM System / 360 . Their micro-architecture was u. a. also reimplemented in a special variant of the Motorola 68000 , the MC68000 / 360. The microprogram of this CPU was modified in such a way that it could execute an S / 360 instruction set. The S / 360 instruction set architecture is today only a subset of the instruction set architectures of IBM's S / 370 and S / 390 series and today's System z architecture.
- MOS Technology : 6502
- Zilog : Z80
- Intel : IA-32 , IA-64
- DEC : Alpha
- ARM : ARM
- Stanford : MIPS
- Sun Microsystems : SPARC
- HP : PA-RISC , IA-64
- IBM : S / 360 , PowerPC
- Motorola : m68k , PowerPC