Network processor

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100 Gbps network processor

A network processor ( English Network Processor , NP , also English Network Processing Unit , NPU ) is a programmable microprocessor that is optimized for processing and forwarding data packets in communication networks.

Network processors can process many packets simultaneously and independently through techniques such as massive parallel processing and pipelining . The resulting wire speed - data transmission rates be at current processors up to 200 Gbit / s duplex (state 2013).

Areas of application

Network processors are used both in the access network ( DSLAMs , base stations , intrusion prevention systems / firewalls , deep packet inspection ) and in the core network ( switches , routers ). Due to their programmability, they can be modified so that new services or protocols can be supported in a short time . In particular, network processors for high bit rate networks are specialized in tasks that are characteristic of layers 2 ( Ethernet ), 3 ( IP ) and 4 ( TCP ) of the OSI network model .

The most important steps in packet processing are (often performed in the order given):

Media Access Control
The Media Access Control takes on functions such as Ethernet framing or ATM cell segmentation and reassembly.
Header parsing and classification
The headers of data packets are parsed and compared with known patterns ( pattern matching ). This means that packets can be classified into different protocols (e.g. VLAN- tagged Ethernet , IPv4 , IPv6 ) and handled accordingly in the course of the process. Packets for network control and monitoring are possibly sent to an external CPU for further processing (control path , "slow path" ).
Access control
Communication is restricted to certain source or destination addresses, for example, via packet filters .
Address learning
If an Ethernet packet has been received, the MAC address of the sender and the associated receiving interface (port number) are entered directly in the Source Address Table (SAT). IP routing tables, on the other hand, are normally updated indirectly via a routing protocol (e.g. BGP , OSPF ).
Table lookup
In order to find out the destination address or the next section , it is necessary to search through an address or routing table . A common search method is the longest prefix match .
Header update
Depending on the protocol, the package is modified in a suitable manner, for example by exchanging an MPLS label or reducing the time-to-live value.
Traffic management / queuing
Based on the previous routing decision, the Traffic Manager controls the traffic flow in such a way that configured Quality of Service (QoS) parameters are adhered to ( traffic shaping , traffic policing ; see also: ATM Traffic Management ). Depending on these quality of service parameters and the individual prioritization, the packets are sorted into different output queues .


In the late 1990s, the data rates and features in IP - routers moved sharply, manufacturers trodden in the packet processing a new way: Programmable Network Tasks specialized processors should defined previously used ASICs replace. The pioneers were the two companies Cisco and Juniper , who used the first self-developed network processors in 2000: Toaster 2 ( Parallel eXpress Forwarding , PXF, Cisco) and Internet Processor II (Juniper). Shortly thereafter, Intel followed suit with the IXP1200, the first freely available network processor.

In the wake of the Internet boom in the second half of the 1990s, dozens of high-tech startups emerged who wanted to build network processors for the new generation of network devices . At the beginning of 2003, 30 different chip manufacturers were already marketing network processors. With the bursting of the dotcom bubble , however, the investment activity of the network operators flagged , which led to the bankruptcy of most network processor providers. As a result, a concentration process set in, which u. a. led to the following acquisitions: Avago / LSI / Agere, Broadcom / Sandburst, Netronome / Intel, Marvell / Xelerated, PMC-Sierra / Wintegra.

The market for freely available network processors is estimated to be US $ 350 million (2012) and has grown more than 6% annually since 2005. Although network processors have found their place as an important building block for network devices, the environment for pure chip manufacturers is challenging as more and more of their large customers are moving to develop network processors themselves.

Architecture and construction

Microarchitecture: parallel processor pipelines
Microarchitecture: pipeline of parallel processors
Microarchitecture: pool of processors

Since the individual tasks involved in processing data packets are relatively simple, most network processors use efficient RISC processors, which are again reduced in their function , which are called processor elements. Common blocks for standard processors such as caches , memory management units (MMU) and floating point units (FPU) are often missing.

Due to the fact that the program flow is strongly linked to the availability of the individual data packets, some network processors are not implemented as command-driven Von Neumann systems . Instead, the (exotic) data flow architecture is used. According to the Flynn classification, it belongs to the class of MISD architectures ( Multiple Instruction, Single Data ).


The goal of high data processing speeds can be achieved not only with fast processor clock rates but also through the basic techniques of parallelization and pipelining . The individual processor elements can each be arranged in different ways. Three typical topologies are presented as examples.

Parallel processor pipelines
One way of combining parallelization and pipelining is the parallel processor pipeline architecture. Incoming packets are assigned to a pipeline, which is then passed through completely. Example: Cisco Toaster.
Pipeline of parallel processors
This architecture variant is similar to a pure pipeline consisting of superscalar processor elements . These can also be of different types. Example: EZChip NP.
Processor pool
A number of identical processor elements are arranged in the form of a pool . A scheduler distributes the data packets to free processor elements. Example: Intel IXP, Alcatel-Lucent FP.

Function blocks

Most network processors have dedicated, hard-coded function blocks to speed up special, computationally intensive tasks. These include engines for hash and CRC calculation, statistics, pattern matching and bandwidth management ( traffic management ). These blocks are not programmable, but can only be configured within narrow limits.

In addition, external coprocessors are often used for support. Examples are general purpose processors (GPPs) for control plane management, knowledge based processors or safety coprocessors.


For reasons of performance, many network processors use efficient, low-level hardware functions. This in turn entails system-level programming in assembler or in the C programming language . The program creation is therefore similar to that of a microcontroller . Few of the available network processors can be programmed in ANSI C using a standard GNU toolchain.


Network processors are differentiated from communication processors and configurable ASSPs .

Communications processor

Communication processors process packets in the data path with comparatively lower bit rates (1–10 Gbit / s). They are therefore cheaper than network processors. Examples are the OCTEON chips from Cavium or the PowerQUICC chips from Freescale . Communication processors have integrated one or more standard ( MIPS , ARM, etc.) processor cores that enable packet processing on the upper network layers (level 4 to level 7) and control protocol processing.

Configurable ASSP

In the area of ​​high data rates, ASSPs compete with network processors. They are only configurable, not programmable, and therefore less complex. Therefore, they are often used for level 2 packet processing ( Ethernet ). Examples are the StrataXGS chips from Broadcom (BCM56xxx).

Manufacturers and Products

Intel FWIXP422BB from the IXP series
  • Alcatel-Lucent - In-house developed network processor chipset (FP series). Since 2011 in the third generation with the FP3, the first processor with 400 Gbit / s throughput simplex .
  • AMCC - market leader until 2005 (nP series), no current products.
  • Avago - With the acquisition of Agere in 2007, LSI Corporation became a supplier of network processors (APP series) used in access networks . In late 2013, LSI was acquired by Avago.
  • Broadcom - Several network processor product lines in the portfolio through various acquisitions, including BCM880xx (Sandburst family) and BCM88650 (Dune). The BCM88030 was the first freely available 100 Gbit / s duplex network processor.
  • Cavium - The OCTEON series is more a communication processor than a network processor and is primarily used in the access network.
  • Cisco - Various self-developed network processors, etc. a. Toaster (2000), Silicon Packet Processor (2007), Quantum Flow (2008) and nPower (2013), the latter with a throughput of 400 Gbit / s simplex.
  • Ericsson - 2013 Presentation of the self-developed SNP 4000 processor with 200 Gbit / s simplex, on which, in contrast to other products, software can be developed under SMP Linux with the GNU C / C ++ toolchain.
  • EZChip - Market leader in high-end, marketable network processors (NP series). With the NP-2 / NP-3, the first 10 Gbit / s network processor with an integrated traffic manager, EZChip has won well-known customers such as Cisco , Juniper , Huawei and ZTE . In production in 2013, the NP-4 is simplex with 100 Gbits / s throughput.
  • Huawei - Solar 2.0 chipset (100 Gbit / s simplex, 2009), Solar 3.0 chipset (200 Gbit / s simplex, 2011).
  • Intel - With the IXP series the pioneer among the manufacturers of network processors for sale. Market leader in 2006, but at the end of 2007 the division was sold to Netronome.
  • Juniper - First manufacturer to develop specific ASICs for packet processing (ABC chipset). As a result, development of various own network processors, u. a. Internet Processor II (2000) and Trio (2009).
  • Marvell - Xelerated, acquired by Marvell in 2012, was the first manufacturer to put a 20 Gbps full duplex network processor in production. Until recently, the processors remained without traffic management functions. Marvell is continuing the special dataflow architecture of the Xelerated processors.
  • Netronome - Market leader in 2007 and beyond with Intel IXP network processors. Further development of the Intel IXP28xx architecture as NFP series.
  • PMC-Sierra - With the acquisition of Wintegra in 2010, market leader in marketable network processors for access networks (WinPath series). Announced customers include Alcatel-Lucent , Cisco and Ericsson .


Web links

Individual evidence

  1. a b Christian Hermsmeyer, Haoyu Song, Ralph Schlenk, Riccardo Gemelli, Stephan Bunse: Towards 100G Packet Processing: Challenges and Technologies ( PDF; 350 kB ( Memento of the original from May 14, 2014 in the Internet Archive ) Info: The archive link became automatic inserted and not yet checked. Please check the original and archive link according to the instructions and then remove this notice. ). Bell Labs Technical Journal, Volume 14, Number 2, Summer 2009, ISSN 1538-7305 , pp. 57-79. @1@ 2Template: Webachiv / IABot / 
  2. ^ A b c d Bob Wheeler, Jag Bolaria: A Guide to Network Processors. Executive summary (web preview). Retrieved March 1, 2014.
  3. ^ A b c Bob Wheeler: A New Era of Network Processing. White Paper ( PDF; 370 kB ). October 2013. Retrieved March 1, 2014.
  4. Craig Matsumoto: How Cisco beat chip world to net. EE Times , October 20, 2000. Retrieved February 23, 2014.
  5. ^ Craig Matsumoto: Intel makes IXP its net processor cornerstone. EE Times , August 25, 2000. Retrieved February 23, 2014.
  6. Douglas Comer: Network Processors: Programmable Technology for Building Network Systems ( PDF; 440 kB ). The Internet Protocol Journal - Volume 7, Number 4, December 2004, ISSN  1944-1134 , pp. 2-12.
  7. a b c Niraj Shah: Understanding Network Processors ( GZIP-PDF; 1.9 MB ). Tech. Report Version 1.0, EECS, University of California, Berkeley, September 2001.
  8. ^ Broadcom: Knowledge-Based Processors. Product information. ( Memento of the original from March 2, 2014 in the Internet Archive ) Info: The @1@ 2Template: Webachiv / IABot / archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. Retrieved March 2, 2014.
  9. Marvell Technology Group: Dataflow Architecture. Product information. ( Memento of the original from July 8, 2014 in the Internet Archive ) Info: The @1@ 2Template: Webachiv / IABot / archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. Retrieved March 1, 2012.