ARM architecture

from Wikipedia, the free encyclopedia
The Arm logo
ARM processor from Conexant , which u. a. in routers is used

The ARM architecture is an originally in 1983 by the British computer company Acorn developed microprocessor design, which of the outsourced from Acorn Company since 1990 ARM Limited is further developed. ARM stood for Acorn RISC Machines , later for Advanced RISC Machines . Although the name is little known outside of the IT professional world , implementations of this type are among the most popular microprocessors in the world.

ARM Limited does not manufacture its own ICs , but grants various licenses to semiconductor development companies and semiconductor manufacturers. Customers can choose between development licenses that enable the development of their own ICs based on the ARM architecture, and the purchase of so-called IP cores , function blocks such as CPU cores of the ARM Cortex-A series, GPU units such as Mali or Bus systems such as AMBA , which are then configured into their own system-on-a-chip components.

The large number of these licensees and various advantages of the architecture (e.g. low energy requirements with high performance) mean that ARM implementations in the embedded area are the most widely used architecture. Almost all smartphones and tablet computers today have licensed ARM processors, including the iPhone and most Android devices. The first ARM processors (ARMv1) from 1985 had a 32-bit architecture ; processors with 64-bit architecture ( ARMv8 series) then appeared around 2013 . The first 64-bit systems were the X-Gene from Applied Micro Circuits Corporation in June 2013 and the A7 in the iPhone 5s in September 2013 .


The ARM design was started in 1983 by the English computer manufacturer Acorn as a development project. Under the direction of Sophie Wilson and Steve Furber, the team began developing a powerful processor for a successor to the computer based on the 6502 up to then .

Instead of using processors from Intel or Motorola like the competition , they developed their own processor, the ARM (Acorn Risc Machine) with 32 bits and a planned clock frequency of 4 MHz. The tests with the prototypes were so successful that the later series processors (ARM2, 1986), which were built into the newly developed computers ( Acorn Archimedes ), were clocked directly at 8 MHz. Tests showed that these computers were about eight times faster than the competitors Commodore Amiga and Atari ST with a Motorola 68000 processor with practically the same clock frequency .

After the ARM2 had been further developed into the ARM3 (with cache and higher clock frequency) in 1989, and more and more companies had expressed interest in these processors, Acorn founded Advanced RISC Machines Ltd. in 1990 together with Apple and VLSI Technology . based in Great Britain, which later became ARM Ltd. was renamed.


The architecture is characterized by an efficient instruction set , allows compact implementation in an ASIC design and is well suited for optimizations in the area of ​​execution speed and power consumption.

A major implementation is the microcontroller known as StrongARM .

The manufacturer Intel , along with other market participants, is a licensee of Advanced RISC Machines Ltd. and is therefore allowed to manufacture processors based on the ARM architecture. In addition, Intel (in addition to e.g. Apple , Motorola / Freescale or NXP ), unlike most other licensees, is allowed to make changes and additions to the ARM core. Until 2006, Intel sold an ARM CPU manufactured under license under the name XScale and other peripheral semiconductors, also known as XScale and connected by bus . These include the PXA250, PXA260 and PXA270 processors, which were often used in PDAs and smartphones , especially for Windows CE and Palm OS .

The GNU Compiler Collection can generate code for ARM and the XNU kernel (macOS / iOS), Linux kernel and Windows NT kernel 6.2 also run on this CPU type.

operation area

Mobile devices

Due to their low power consumption , ARM processors are mainly used in embedded systems such as cell phones , PDAs and routers . The architecture is particularly important for smartphones , as it is supported by all common mobile operating systems. There is a similar prevalence in portable game consoles . The CPUs can also be found in many stationary devices in entertainment electronics .

Workstation computer

The computers of the Acorn Archimedes and Risc PC series from Acorn also used ARM CPUs. Successor models of these desktop computers were available from Castle Technology under the name IYONIX pc .

IoT devices

Also on the Raspberry Pi a is a single-chip system by Broadcom with an ARM microprocessor installed.


With the completion of the 64-bit ARMv8 micro-architecture in 2012, the prerequisites for the use of ARM processors in server systems were given. ARM was faced with the task of defining a complete market segment, since server systems also require specialized operating systems and applications. With the cooperation of Red Hat and other operating system manufacturers, the Server Base System Architecture ( SBSA ) was created in 2016 , a specification that includes all hardware interfaces that are required on a server system for the operating system. This resulted in ARM Linux server distributions from Red Hat, SuSE and Ubuntu as well as a Windows ARM server variant from Microsoft, which in turn provide a basis for important infrastructure applications. The ARM architecture is also interesting for this market segment because of its low power consumption (price / watt and price / performance index), which is why ARM also advertises server processors for high-performance computers and supercomputers .

Several partners (architecture licensees) then developed ARM server processors:

In autumn 2018, ARM will then publish its own roadmap on technologies for server processors, called Neoverse . This documents that further ARM developments and support for the development partners can be expected.

Instruction set and programming model

The ARM CPU is a RISC architecture and as such knows three categories of commands:

  • Commands to access the memory (Load / Store),
  • arithmetic or logical commands for values ​​in registers,
  • Commands for changing the program flow (jumps, subroutine calls).

The ARM uses a three-address code instruction set, so all arithmetic-logic instructions accept one destination register and two operand registers.

ADD  r0, r1, r2   ;r0 := r1 + r2

The ARM is both little-endian and big-endian compatible, i.e. it can handle both byte orders, which is a clear advantage in view of its intended use as a standard CPU in communication devices. The standard mode of the ARM is little-endian.

Data and code (BE32)
  • ARMv4
  • ARMv5
  • ARMv6
Data only (BE8)
  • ARMv6
  • ARMv7
  • ARMv8

Register set

Like many RISC CPUs, ARM offers a large number of registers, although the PowerPC has about twice as many. The programmer has 13 general-purpose register available r0... r12. Three additional registers r13... r15are addressable like universal registers, but have specific meanings. These are a stack pointer r13 , a "link register" r14that contains the return address for procedure calls (with BL"branch with link"), which is later written back to the program counter, as well as the program counter (program counter, PC) itself r15. In addition to these directly changeable registers, there is the status register ( CPSR, Current-Program-Status-Register), which contains the status bits and other information, such as B. the current execution mode contains.

Execution modes

The ARM knows several execution modes, which are entered via certain events and in some cases grant the executed code additional privileges. In detail these are:

  • User mode: normal user code
  • Supervisor mode (SVC): privileged operating system tasks, entry e.g. B. by calling a software interrupt (SWI)
  • Hypervisor mode (HYP): privileged tasks for fulfilling hypervisor functions
  • Interrupt mode (IRQ): Entry when an external interrupt request occurs during command processing
  • Fast-Interrupt-Mode (FIQ): Entry when an external Fast-Interrupt request occurs. Fast interrupts are mostly only used for particularly time-critical events (see real-time systems ).
  • Memory Abort (ABT): occurs when a data request cannot be fulfilled.
  • Undefined instruction exception (AND): Occurrence when an unknown instruction occurs. Is z. B. used to emulate a floating point coprocessor .

r13, r14and the status register are mirrored for the interrupt and exception modes (so-called shadow registers), so that exception handling routines do not have to worry about saving the user stack pointer or link register. For the fast interrupts r8... are also r12mirrored and are thus directly available to the programmer of an interrupt service routine without having to save the content of these registers beforehand.

Command width and addressing types

The ARM's Load / Store command supports the usual addressing modes. With direct addressing and absolute addressing, however, there are some restrictions that are explained in more detail below:

All commands in the ARM command set are 32 bits long. On the one hand, this means that each instruction can be loaded with a memory access, which simplifies the design of the pipeline and the instruction fetch unit. On the other hand, 32-bit addresses or 32-bit values ​​cannot be specified in a 32-bit wide command, since there is then no more space for the actual command code. Instead, you can help yourself as follows:

  • No arbitrary 32-bit values ​​can be coded directly in the command. Instead, 8 mantissa bits and 4 shift bits are specified for direct values, whereby the actual shift value is twice the stored value, i.e. bit shifts of 0, 2, 4, 6, 8, ..., 26, 28 and 30 digits are possible respectively. The bits that are shifted out of the register are shifted back in on the other side. If this technique z. As applied to the value 255 in the mantissa bits, the hexadecimal values 000000FF, 000003FC, 00000FF0, 00003FC0, ... 0FF00000, 3FC00000, FF000000, FC000003, F000000Fand C000003Fare encoded directly.
  • Other values ​​can be generated by a combination of arithmetic operations (e.g. addition, subtraction).
  • Alternatively, values ​​can also be held in memory and loaded into a register before the actual command.
  • The (relative) jump instruction contains a 24-bit offset so that a jump can be made in the range of ± 32  MiB from the current position in the program (whereby the program counter leads the current instruction by 8 bytes). In addition, the current program counter can optionally be copied into the link register (if the L bit is set), so that the jump becomes a subprogram call (the called function can simply copy MOV PC,LRthe program counter from the link register back into the program counter register in order to return to the calling Program).
  • With the load / store commands, a 12-bit offset can be added to a base address that is read from a register. If the program counter is used as a base register, such a value can be loaded within 4  KiB of the current position in the program. This z. B. execute a jump to any 32-bit address by storing the absolute jump address after the load command and then jumping to the target program counter with a PC-relative load command LDR PC,[PC,#-4].
  • All memory locations that are outside of the 4 KiB around the current location in the program can only be loaded by first loading their address into a register and using this as the base register in subsequent accesses.

Special features of the instruction set

The ARM instruction set contains some special features that contribute to the efficiency of the architecture:

  • Practically all commands can be executed conditionally ("conditional execution"). This eliminates the need for program jumps in many standard situations, e.g. B. in many If / Else queries (program jumps are avoided because they empty the pipeline of the processor and this creates waiting cycles). The first 4 bits of each command in the machine code or a suffix in the mnemonic are used to code the condition.
CMP    r0, r1            ;(setzt Bedingungsbits)            ; "CMP" bedeutet:   "CoMPare"
ADDGE  r2, r2, r3        ;if r0 >= r1 then r2 := r2 + r3    ; "ADDGE" bedeutet: "ADD if Greater or Equal"
ADDLT  r2, r2, r4        ;            else r2 := r2 + r4    ; "ADDLT" bedeutet: "ADD if Less Than"
  • 1111At the beginning, the condition code stood for the condition NV(never), so these commands are never executed. These opcodes are used in newer CPUs for special commands such as PLDand BLX(which can then no longer be executed conditionally). The use of any opcodes with a condition NVfor NOPs is therefore not recommended ("deprecated").
  • Optionally, the status bits can be updated as a result of the command. This is indicated by the suffix Sin the assembler code and can be combined with the conditional execution.
CMP    r0, r1            ;(setzt Bedingungsbits)
ADDGES r2, r4, r5        ;if r0 >= r1 then r2 := r4 + r5
BCS    overflow          ;verzweige bei Überlauf der Addition
  • The ARM has a barrel shifter in the B path of the ALU; all commands that work with the second operand allow a 4-bit wide shift or roll factor to be specified.
ADD  r2, r3, r3, lsl #2  ;r2 := r3 + (r3 << 2)
                         ;   := r3 + 4*r3
                         ;   := 5*r3
  • Newer ARM CPUs know SIMD commands.

Thumb instruction set

In order to increase the code density, i.e. to reduce the memory requirement for a certain function, ARM Ltd. developed the Thumb instruction set, which only consists of 16 bit wide instructions. Although it often takes more assembly language instructions to write a program, in practice the code size is reduced by about 30 to 40 percent. Instructions are loaded from 16-bit memory modules in just one memory cycle; an ARM processor always loads two thumb instructions from 32-bit memory modules.

However, the smaller program size is often bought at the price of a lower execution speed. On the one hand, many thumb commands are less powerful than the corresponding ARM commands (and more thumb commands are required); on the other hand, there is no conditional command execution in this 16-bit command set other than the conditional jumps. Therefore, more program jumps occur and the pipeline is emptied more often. At least when the memory is addressed with 32 bits, the 16-bit instruction set is often slower than the ARM instruction set. The manufacturer NXP states in the data sheets of its LPC2000 controllers a speed loss of 30 percent.

ARM and thumb code can be mixed together. The speed of execution is often secondary in large parts of a program. It is advisable to use Thumb instructions for these program parts, but to implement the critical areas with ARM instructions. This technique is called thumb interworking .

Coprocessor commands

The ARM is intended as a microprocessor core in embedded systems, in which floating point arithmetic is usually not required. However, the ARM was specially developed with a view to expandability with coprocessors and has its own coprocessor interface and commands for optional coprocessors.

Big.LITTLE concept

Together with the Cortex-A 7, ARM introduced the Big.LITTLE concept, which is used to combine the high computing power of the Cortex-A15 with 3.5  DMIPS / MHz with the low energy consumption of the Cortex-A7. Both cores are combined in the form of clusters with two to four cores each on one SoC . Since the Cortex-A7 looks like a Cortex-A15 from a software point of view, the Cortex-A15 cluster is switched off for tasks that do not require full computing power and the other calculations are carried out by the Cortex-A7. If more computing power is required, the Cortex-A15 cluster is switched on again and the Cortex-A7 cluster is shut down. After the appearance of the 64-bit CPUs Cortex-A 53 and A57, the Big.LITTLE concept was also transferred to them. At the same time, it has been expanded so that tasks can now be transferred not just cluster-wise, but individually from any CPU to any other. However, the concept suffers from some weaknesses, such as: B. in the case of sudden load changes that result in high latency times, or if the real energy consumption of the individual CPUs is not taken into account.


In 2017, ARM expanded the Big.LITTLE concept in several points: and

  • In DynamIQ, up to 6 clusters of different or the same CPU cores can work together, any "mixtures" can be connected
  • the cores are coupled to the cache coherent interconnect ( CCI ) called CoreLink with lower latency , all clusters can access the level 3 cache, so tasks can be distributed to several clusters at the same time.
  • Up to 24 cores can be connected
  • Up to 6 main memory channels can be connected
  • The clusters and individual cores can be operated with different frequencies and voltages, which leads to higher energy efficiency
  • In addition to Cortex-A CPU cores, other "accelerators" can also be connected

The DynamIQ CCI units are offered for SoCs only with the 64-bit cores A55, A75, A76 and A77 together.


ARM 1 CPU in an Acorn ARM Evaluation System
The one ARM610 microprocessor.

The architecture of ARM processors has undergone numerous changes since 1985, for example in the number of registers, the size of the address space and the scope of the instruction set. It is therefore divided into versions, abbreviated to ARMv [version number]. Starting with ARMv2, the architectural versions were implemented in more than just one processor design.

Since the ARMv6, the so-called Cortex architectures have been specially developed for special applications:

  • Cortex A stands for Application (operating system-based applications),
  • Cortex M stands for microcontroller (cores for microcontroller), and
  • Cortex R stands for Realtime (real-time applications).


ARM design (s) / family (s) Release
Usual CPU
speed (MHz)
Command throughput
( DMIPS / MHz)
ARMv1 ARM1 1985 0004th -
ARMv2 ARM2, ARM3 1986, 1989 0008 ... 25 0.5
ARMv3 ARM6, ARM7 1991, 1993 0012 ... 40 0.89
0016.8 ... 75
0203 ... 206
2002 0104 ... 369
0133 ... 1250
ARMv6 ARM11 (1176, 11 MPCore, 1136, 1156)
ARM Cortex-M (M0, M0 +, M1)
0427 ... 1000+
to 200
0.6 0..1.54
0.84 [0]... 0.94
ARMv7 ARM Cortex-A (A8, A9, A5, A15, A7, A12, A17)
ARM Cortex-M ( M3 , M4 , M7 )
ARM Cortex-R (R4, R5, R7, R8)
until 2500.
? 1.25 ... 2.14 ?0
ARMv8 ARM Cortex-A (A32, A53, A57, A72, A35, A73, A55, A75, A76, A77)
ARM Cortex-M (M23, M33)
ARM Cortex-R (R52)
1200 ... 3000.

ARMv1 (1985)

The first versions of an ARM processor (ARMv1) were used in 1985 as a second processor in the ARM Development System for the BBC Master .

ARMv2 (1986)

The ARMv2 architecture comprises two families: ARM2 and ARM3.

The ARM2 is developed by the English company Acorn Computers Ltd. developed 32-bit - RISC - processor . This was published in 1986 and used in the Acorn Archimedes from 1987 . At the standard clock of 8  MHz , an unbelievable 4 MIPS was achieved for the time  . In 1991 the ARM250 appeared, which was also based on the ARM2, but was now clocked at 12 MHz and reached 7 MIPS. In addition, an MMU unit as well as a graphics and IO processor have been integrated. This CPU was only used in the Archimedes models A3010, A3020 and A4000.

The ARM3 is also a 32-bit RISC processor developed by Acorn Computers Ltd. was developed. It was released in 1989 and used in the Archimedes models A540, A5000 and A4. In this processor, Acorn has integrated a cache with 4 KiB for the first time . With a clock frequency of 25  MHz , the ARM3 achieves 12  MIPS .

ARMv3 (1991)

The ARM6 is one of the now established ARM Limited published 1991 32-bit RISC - processor , the CPU as for example in the Apple Newton or Acorn Risc PC was used. The CPU clock was 12–33 MHz.

ARMv4 (1993)

32-bit ARM 60 RISC in a 3DO game console FZ-10 (1993)

The ARM7TDMI was the low-end model of the ARM family and was mainly used as a component in SoCs for cell phones and other portable communication or multimedia devices, including the Game Boy Advance , Nintendo DS (as a subprocessor) and Nintendo 3DS (also as Subprocessor). The abbreviations in the model names stand for T Humb instruction set (program memory efficient 16-bit mode of the 32-bit core), D ebug port 64-bit Result M ultiplier and Embedded I CE module.

The ARM7TDMI has a three-stage pipeline and a common bus for instructions and data.

The ARM StrongARM , developed together with DEC , was the first spin-off of the ARM architecture, which in 1995 as SA-110 in Newton 2000 ensured long battery life through a power-saving mode. The successor SA-1100 (1997) was one of the first system-on-a-chip with an LCD interface, an MCP audio / touchscreen interface, PCMCIA support, IrDA, USB and DMA controller .

ARMv5TE (1997)

The architecture version 5TE was implemented by ARM in the processor models ARM7EJ, ARM9E and ARM10E. ARM9 is a further development of the StrongARM and ARM8 processors. The main difference between the ARM9 and the ARM7 is a separate bus for instructions and data ( Harvard architecture ). Usually these are connected to separate caches for data and instructions. In addition, the ARM9 has a five-stage pipeline and can thus achieve higher clock rates and has better CPI values ​​(Cycles per Instruction). If the ARM9 is operated without caches on an external memory with only one data bus, the speed advantage compared to the ARM7 design shrinks due to frequent pipeline stalls with a higher "penalty" due to the longer pipeline. Without a cache, an ARM7 can be faster in such an unfavorable scenario due to its shorter pipeline despite a significantly lower clock rate. However, this case should not occur in real systems, since an ARM9 is more expensive and is only selected because of its better performance. If the cost is more important, then it makes sense not to save on the cache, but use an ARM7.

Starting in 2002, Intel introduced the processors of the XScale series (802xx, PXA25x, XA263, PXA26x, PXA27x, PXA3xx) based on the ARMv5TE, which can be used in many mobile devices ( Palm Tungsten , Sony Clié ) with a clock frequency of up to 1250 MHz. Found entrance. In 2006 the XScale development was sold to the Marvell Technology Group . In June 2008, Marvell presented the Sheeva microprocessor based on the ARMv5TE . This is intended as the main processor for integration into the in-house one-chip systems . A SoC with Sheeva CPU developed by Marvell forms the basis for the first “ plug computer ” brought to market . The so-called SheevaPlug was presented in 2009.

ARMv6 (2002)

With ARMv6, announced in October 2001, SIMD instructions were added, multi-processor support and a new cache architecture. Implementations of this architecture version are the ARM11 family, which has also set itself apart from the ARM9 and ARM10 families thanks to an improved pipeline, and the smaller processor cores for microcontrollers ARM Cortex-M 0, ARM Cortex-M0 + and ARM Cortex-M1.

ARM11 cores - the first, ARM1136, was offered to licensees in October 2002 - have been built into smartphones, including from Apple and Nokia.

ARMv7 (2004)

A SIMD unit is introduced that works with 32 registers of 128 bit width, called NEON , primarily intended for multimedia processing, but which, like competing SIMD units ( AltiVec / VSX in the POWER architecture or SSE / AVX in the Intel Architecture) can execute a variety of arithmetic and vector instructions.

As of the ARMv7 architecture, the processor cores implementing them are assigned to three application fields:

  • ARM Cortex-M : The letter M stands for the designation English microcontroller (dt. Microcontroller applications ). Typical application in non-time-critical control and regulation tasks. Cortex-M microcontrollers are available from many manufacturers and are characterized by a wide range of input and output interfaces.

ARMv8-A (2011)

The eighth version of the ARM architecture was presented in October 2011. With ARMv8-A, ARM implemented a 64-bit architecture for data processing and memory addressing for the first time . The compatibility with the existing 32-bit software should be maintained. ARMv8 is backwards compatible up to ARMv5. There are two independent execution modes: AArch32 for processing 32-bit software and AArch64 for processing 64-bit software. A new instruction set - called A64 - is used in AArch64 mode, while AArch32 mode supports the conventional ARM instruction set. With ARMv8-A, ARM made VFPv3 / v4 and SIMD (NEON) mandatory and added cryptography instructions for AES and SHA-1 / SHA-256.

In October 2012, ARM introduced the Cortex-A53 and Cortex-A57, the first processor designs to implement ARMv8. The first third-party implementation of the ARMv8 was for the CPU cores of the X-Gene - SoC from Applied Micro Circuits Corporation (AMCC). X-Gene was presented in June 2013 and is marketed by the manufacturer as a “ server -on-a-chip” solution. The first mobile device with an ARMv8-based SoC is the iPhone 5s introduced in September 2013 . The built-in SoC integrates two CPU cores designed by Apple called Cyclone . Qualcomm developed the Kryo CPU design based on ARMv8 . A SoC with such CPU cores was first presented in 2015. Qualcomm promises higher performance and energy efficiency for Kryo compared to the ARM Cortex-A57.

ARM developed several enhancements for ARMv8-A: ARMv8.1-A (December 2014), ARMv8.2-A (January 2016), ARMv8.3-A (October 2016), ARMv8.4-A (November 2017), ARMv8 .5-A (September 2018) and ARMv8.6-A (August 2019).

Extensions for ARM cores

ARM Ltd. In addition to ARM CPU cores, it also sells expansions as synthesizable macro cells for SoC design, including memory management units , floating point coprocessors and signal processor expansions (Piccolo).


The following companies have the ARM architecture from ARM Ltd. licensed:

See also


  • Steve Furber: ARM System-on-Chip Architecture . Addison-Wesley, New York 2000, ISBN 0-201-67519-6 .

Web links

Commons : ARM microprocessors  - collection of images, videos and audio files

Individual evidence

  1. Dan Grabham: From a small Acorn to 37 billion chips: ARM's ascent to tech superpower in Techradar.
  3. a b Charlie Demerjian: AMCC X-Gene 64-bit silicon spotted in the wild . SemiAccurate. Retrieved June 14, 2013.
  4. a b Anand Lal Shimpi: Apple Announces A7, World's First 64-bit Smartphone SoC. Announced at on September 10, 2013.
  8. ^ ARM Information Center. Retrieved March 1, 2018 .
  9. Frank Riemenschneider : Cortex-A15 is aimed at the communication and server market . In: . March 10, 2011. Archived from the original on May 9, 2015. Retrieved on August 8, 2013.
  10. Frank Riemenschneider : ARM pairs Cortex-A7 and Cortex-A15 . In: . June 13, 2012. Archived from the original on September 23, 2015. Retrieved on August 8, 2013.
  11. a b Frank Riemenschneider : Qualcomm's Snapdragon 810 is better than ARM despite ARM . In: . Archived from the original on September 23, 2015. Retrieved March 3, 2015.
  14. a b ARM: ARM11 Processor Family .
  15. ARM: ARM 1176 Processor .
  16. Cortex-M1 Processor at, accessed July 23, 2012.
  17. ^ ARM: ARM 1156 Processor
  18. a b Stephen Barret: Cortex-M7 Launches: Embedded, IoT and Wearables In: AnandTech , September 23, 2014.
  19. Preetam: MediaTek To Announce 2.5 GHz Octa-Core MT6595 Chipset, Scores 43,000 in AnTuTu. (No longer available online.) In: NEXTPOWERUP. July 14, 2014, archived from the original on September 8, 2015 ; accessed on August 28, 2015 .
  20. Atmel: SMART SAMA5 ARM Cortex-A5 MPUs
  21. Texas Instruments: KeyStone II - ARM Cortex-A15 - CorePac Overview
  22. ARM Launches Cortex-A50 Series, the World's Most Energy-Efficient 64-bit Processors . October 30, 2012. Retrieved October 29, 2013.
  23. Sylvie Barak: ARM Announces ARMv8A-Based Cortex-A72, 16nm FF + Process, Mali-T880 GPU. In: tom's hardware. February 3, 2015, accessed August 28, 2015 .
  24. Nermin Hajdarbegovic: ARM: Shift to 64-bit SoCs accelerating In: , April 24, 2014.
  25. Frank Riemenschneider: ARM reveals new 64-bit cores In: , October 30, 2012.
  26. Marvell: Marvell Sheeva Embedded CPU Technology Set to Drive Next Generation of Consumer, Mobile and Enterprise Applications , press release of June 2, 2008.
  27. ARM: ARM Discloses Technical Details Of The Next Version Of The ARM Architecture , press release of October 27, 2011.
  28. Frank Riemenschneider : ARMv8 architecture: From 32 to 64 bit . In: . February 27, 2012. Retrieved August 8, 2013.
  29. Frank Riemenschneider: ARM reveals new 64-bit cores. In: , October 30, 2012. ( Memento from March 4, 2016 in the Internet Archive )
  30. Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute. In: September 2, 2015 (English).
  31. ^ The ARMv8-A architecture and its ongoing development
  32. ARMv8-A architecture evolution
  33. Armv8-A architecture: 2016 additions
  34. Introducing 2017's extensions to the Arm Architecture
  35. Arm A-Profile Architecture Developments 2018: Armv8.5-A
  36. BFloat16 extensions for Armv8-A ( en ) Accessed August 30, 2019.
  37. AMD to License ARM for Future Opteron Server Chips
  38. Frank Riemenschneider : XMC1000: Peripheral miracle with Cortex-M0 . In: . January 8, 2013. Retrieved August 8, 2013.
  39. Microsoft buys ARM license
  40. Nvidia buys ARM license
  41. The implementation of the Cortex-A8 design called " Hummingbird " is used, for example, in Galaxy smartphones : Samsung's "Hummingbird" smartphone processor with 1 GHz on July 27, 2009.
  42. Only Cortex-A15, Cortex-A57 and Cortex-A72 are affected according to