Scalable vector extensions

Scalable Vector Extension or SVE for short is the name of a specification for SIMD units within the ARM processor architecture . The specification was developed as an extension of the 8th generation ( ARMv8 , a 64-bit processor architecture) of this processor architecture and should allow SIMD commands up to a width of 2048 bits to be defined in 128-bit steps. SVE is not compatible with Neon (an older SIMD unit for ARM processors), but defines a new instruction set within the ARM64-bit instruction set, primarily intended for high performance computing. The specification only defines the instruction set and registers regardless of the actual implementation. The width of the execution units can range from 128 bits to 2048 bits in 128-bit steps, the instruction set is independent of the physical implementation, SVE code can thus be executed on future, more advanced SIMD units (larger width) without code changes or recompilation.

SVE works like neon with 32 registers (different widths), but also requires vector control registers that specify the vector length and property registers

Web links

• Specification from SVE: https://developer.arm.com/-/media/developer/products/architecture/DDI0584A_d_SVE.zip
• Description of SVE for the HotChips conference 2016 by Nigel Stephens: https://community.arm.com/processors/b/blog/posts/technology-update-the-scalable-vector-extension-sve-for-the-armv8- a-architecture

The first implementation of an SVE unit was built by Fujitsu-Computer for their Post-K or Fugaku (supercomputer) , the A64FX chip.