ARM Cortex-M

ARM Cortex-M is a family of IP cores primarily for 32-bit - microcontroller , which the company ARM is licensed and is being developed to several manufacturers. The core is a Reduced Instruction Set Computer (RISC), is part of the ARMv6 or ARMv7 architecture and is divided into the units Cortex-M0, Cortex-M0 +, Cortex-M1, Cortex-M3, and Cortex in increasing complexity -M4, Cortex-M7 and the ARMv8 architecture- based Cortex-M23, and Cortex-M33.

ARM Cortex-M0 and M3-based microcontrollers from NXP and Silicon Laboratories

General

ARM Limited does not manufacture any microprocessors or microcontrollers itself, but licenses the core to manufacturers and chip producers, so-called integrated device manufacturers (IDM), who add their own and manufacturer-specific peripherals such as B. Controller Area Network (CAN), Local Interconnect Network (LIN), Universal Serial Bus (USB), I²C bus, Serial Peripheral Interface (SPI), serial interfaces , Ethernet interfaces, pulse width modulation outputs, analog-to-digital converters , Universal Asynchronous Receiver Transmitter (UART) and many more. These units are connected to the ARM core via the Advanced Microcontroller Bus Architecture (AMBA). ARM Limited offers different license models for the core, which differ in the cost and scope of the data provided. In all cases, you have the right to freely sell your own hardware with ARM processors.

The "ARM Cortex-M" processors are available to the licensee as an IP core in the hardware description language Verilog and can be mapped as digital hardware circuit using logic synthesis , so that they can be used either in field programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). to be used. Depending on the license model, either the use of the IP core is permitted (IP core license) or a completely new, own microarchitecture can be developed that implements the ISA from ARM (architecture license). If you have both licenses, you can also expand and change the IP cores. The advantages of the architecture license are that, in addition to the integration of their own peripherals, manufacturers can also make other extensions such as their own machine commands , integration of special debug interfaces or optimization for a specific purpose (such as mobile devices) based on their own architecture.

Instruction set

The processors Cortex-M0 and M1 are based on an ARMv6-M architecture, the Cortex-M3 on an ARMv7-M architecture, and the Cortex-M4 and Cortex-M7 on an ARMv7E-M architecture. The differences primarily concern the instruction set and the available machine instructions. The lines are defined in such a way that the binary machine commands are upwardly compatible, i.e. a machine program from a Cortex-M0 or M1 can also run on a Cortex-M3, M4 or M7 without modification. Conversely, not all commands of the Cortex-M3, M4 or M7 can be executed on the Cortex-M0 or M1.

All processors from the Cortex-M family support the basic instructions from the so-called Thumb instruction set , the Thumb-2 instruction set, and also offer a hardware multiplier unit . M0 and M1, however, are missing newer extensions in the Thumb command set, such as the commands CBZ , CBNZ and IT , which are only available in the later developed ARMv7-M architecture. And the Thumb-2 command set is limited to a few commands such as BL , DMB , DSB , ISB , MRS and MSR . The restrictions for M0 and M1 are a result of the requirement to keep the chip area as small as possible.

Cortex-M3, with a larger chip area, includes the complete Thumb and Thumb-2 instruction set, also offers some special instructions, its own division unit in hardware and can handle mathematical instructions such as addition instead of overflow with saturation , which is especially true in the area the signal processing is important. Cortex-M4 extends these possibilities with some special commands, as they are common with digital signal processors (DSP), and optionally offers a floating point unit for processing floating point numbers according to the IEEE 754 standard for simple accuracy . The Cortex-M7 extends the floating point unit for manipulating floating point numbers for double precision .

Cortex-M family, instruction sets

ARM Cortex-M	Thumb	Thumb-2	Hardware multiplier	Hardware divider	DSP extension	Saturation arithmetic	Floating point unit	TrustZone	ARM architecture
Cortex-M0	Mostly	Subset	1 or 32 cycles	No	No	No	No	No	ARMv6-M
Cortex-M1	Mostly	Subset	3 or 33 cycles	No	No	No	No	No	ARMv6-M
Cortex-M3	Completely	Completely	1 cycle	Yes	No	partially	No	No	ARMv7-M
Cortex-M4	Completely	Completely	1 cycle	Yes	Yes	Yes	Optional	No	ARMv7E-M
Cortex-M7	Completely	Completely	1 cycle	Yes	Yes	Yes	Optional	No	ARMv7E-M
Cortex-M23	Completely	Completely	1 cycle	Yes	Yes	No	No	Yes	ARMv8-M
Cortex-M33	Completely	Completely	1 cycle	Yes	Yes	Yes	Optional	Yes	ARMv8-M

ARM Cortex-M options

Type	SysTick timer	Bit banding	Memory Protection (MPU)
Cortex-M0	Optional	No	No
Cortex-M1	Optional	No	No
Cortex-M3	Yes	Optional	Optional
Cortex-M4	Yes	Optional	Optional
Cortex-M7	Yes	Optional	Optional

Most Cortex-M3 and -M4 chips offer bit banding . This means that certain bits in the memory can be mapped to their own word address and can therefore be addressed more easily. It is not to be confused with bit banging . However, whether the function actually exists on a specific Cortex-M implementation should be checked on a case-by-case basis.

Types

Cortex-M0

particularities

Special features of the Cortex-M0 are:

• ARMv6-M architecture
• Von Neumann architecture (different from M3 and M4)
• Wake-up interrupt controller
• Instruction set
  • Thumb - almost completely except for CBZ, CBNZ, IT.
  • Thumb-2 - subset consisting of BL, DMB, DSB, ISB, MRS, MSR.
  • 32-bit multiplication unit, selectable for synthesis with one cycle, which requires a larger chip area, or with 32 cycles and less chip area.
• 3-stage pipeline

Implementations

Among others, the following semiconductor manufacturers offer Cortex-M0 based microcontrollers:

• Infineon : XMC1000 family
• NuvoTon : NuMicro family
• NXP : LPC11xx and LPC12xx families
• STMicroelectronics : STM32-F0 family
• Toshiba : TX00 family

Cortex-M0 +

particularities

Special features of the Cortex-M0 + are:

• ARMv6-M architecture
• Von Neumann architecture (different from M3 and M4)
• Wake-up interrupt controller
• Interrupt vector table shift into RAM
• Instruction set
  • Thumb - almost completely except for CBZ, CBNZ, IT.
  • Thumb-2 - subset consisting of BL, DMB, DSB, ISB, MRS, MSR.
  • 32-bit multiplication unit, selectable for synthesis with one cycle, which requires a larger chip area, or with 32 cycles and less chip area.
• 2-stage pipeline

Implementations

The following semiconductor manufacturers, among others, offer Cortex-M0 + based microcontrollers:

• Atmel : SAM D20 / 21 and SAM D10 / 11 family
• Freescale: Kinetis KL family
• NXP : LPC800 family
• Renesas: Synergy Family (S1)
• Silicon Laboratories : Zero-Gecko Family (EFM32ZG)
• Spansion / Cypress : FM0 + family
• STMicroelectronics : STM32L0 family

Cortex-M1

particularities

Special features of the Cortex-M1 are:

• ARMv6-M architecture
• Instruction set
  • Thumb - almost completely except for CBZ, CBNZ, IT.
  • Thumb-2 - subset consisting of BL, DMB, DSB, ISB, MRS, MSR.
  • 32-bit multiplication unit, selectable for synthesis with one cycle, which requires a larger chip area, or with 32 cycles and less chip area.

Implementations

Among others, the following semiconductor manufacturers of Field Programmable Gate Array (FPGA) offer so-called soft cores for their logic components:

• Actel FPGAs
• Altera FPGAs
• Xilinx FPGAs

Cortex-M3

→ Main article : Cortex-M3

Cortex M3 in a microcontroller from NXP , type LPC1768

particularities

Special features of the Cortex-M3 are:

• ARMv7-M architecture
• Instruction set
  • full thumb instruction set
  • complete Thumb-2 instruction set
  • 32-bit multiplying unit with one cycle, 2 to 12 cycle long division instructions, mathematical functional unit with overflow or saturation properties.
• 3-stage pipeline with branch prediction
• 1 to 240 physical hardware interrupt , a special form of interrupt with 12 cycles of latency.
• Various standby modes (sleep modes)
• Memory Protection Unit (MPU) with 8 regions as an option
• 1.25 DMIPS per MHz clock frequency
• can be produced with 90 nm semiconductor technology.
• 32 µW per MHz clock frequency
• Area on the chip for the core: 0.12 mm²

Implementations

Among others, the following semiconductor manufacturers offer Cortex-M3 based microcontrollers:

• Actel : SmartFusion family
• Atmel : SAM3 family
• Cypress Semiconductor : PSoC 5
• NXP : LPC13xx, LPC15xx, LPC17xx, LPC18xx families
• Silicon Laboratories : Tiny Gecko (EFM32TG), Gecko (EFM32G), Leopard Gecko (EFM32LG) and Giant Gecko Families (EFM32GG)
• Spansion / Cypress : FM3 family
• STMicroelectronics : STM32 F2, F1, L1, W families
• Texas Instruments : Stellaris, TMS470, and some processors from the OMAP4 family
• Toshiba : TX03 family

Cortex-M4

→ Main article : Cortex-M4

particularities

The structure of the Cortex-M4 corresponds to an M3, which is extended by special DSP commands and optionally a floating point unit . Cortex-M4 with floating point unit is called Cortex-M4F. Special features of the Cortex-M4 are:

• ARMv7E-M architecture
• Instruction set
  • full thumb instruction set
  • complete Thumb-2 instruction set
  • 32-bit multiplying unit with one cycle, 2 to 12 cycle long division instruction, mathematical functional unit with overflow or saturation property.
  • DSP extensions: 16/32-bit MAC command with one cycle, 8/16-bit SIMD arithmetic.
  • optional floating point unit with the designation FPv4-SP , IEEE-754 compatible.
• 3-stage pipeline with branch prediction
• 1 to 240 physical hardware interrupt , a special form of interrupt with 12 cycles of latency.
• various standby modes ( sleep modes )
• Memory Protection Unit (MPU) with 8 regions as an option
• 1.25 DMIPS per MHz clock frequency (1.27 DMIPS / MHz with FPU )

Implementations

Among other things, the following semiconductor manufacturers offer Cortex-M4 based microcontrollers:

• Atmel : SAM4 family (Cortex-M4)
• Freescale : Kinetis family (Cortex-M4 and Cortex-M4F)
• Infineon : XMC4000 family (Cortex-M4F)
• NXP : LPC40xx and LPC43xx families (Cortex-M4)
• Silicon Laboratories : Wonder Gecko Family (EFM32WG, Cortex-M4F)
• Spansion / Cypress : FM4 family (Cortex-M4F)
• STMicroelectronics : STM32-F4, L4, F3, G4 families (Cortex-M4F)
• Texas Instruments : Stellaris-LM4F and Tiva-TM4C family (Cortex-M4F)
• Toshiba : TX04 family (Cortex-M4F)

Cortex-M7

particularities

Compared to the Cortex-M4, the M7 has a longer dual issue pipeline for higher clock frequencies, a newly designed storage system and the like. a. equipped with L1 caches and TCMs, a doubling of the DSP performance compared to the M4 and an optional lock-step operation. Special features of the Cortex-M7 are:

• ARMv7E-M architecture
• Instruction set
  • full thumb instruction set
  • complete Thumb-2 instruction set
• L1 caches for instructions and data of 4–64 kB each
• TCM for commands and data each 0–16 MB
• a total of 6 memory interfaces, of which 2 × 64 bit and 4 × 32 bit
• 32-bit multiplying unit with one cycle, 2 to 12 cycle long division instruction, mathematical functional unit with overflow or saturation property.
• DSP extensions: 16/32-bit MAC command with one cycle, 8/16-bit SIMD arithmetic.
• Floating point unit with the designation FPv5 , IEEE-754 compatible, with instructions for single precision (32 registers á 32 bit) or optionally, depending on the implementation, also double precision (16 registers á 64 bit).
• 6-stage dual issue pipeline with branch prediction
• 1 to 240 physical hardware interrupt , a special form of interrupt with 11–12 cycle latency.
• various standby modes ( sleep modes )
• Memory Protection Unit (MPU) with 8 or 16 regions as an option
• Lock-step operation with two independently working cores
• maximum clock frequency when manufactured in a 40 nm LP process 400 MHz
• 2.14 DMIPS per MHz clock frequency

Implementations

So far only Atmel, ST Microelectronics and NXP Cortex-M7 based microcontrollers offer:

• Atmel : SAM S-, E- and V-series
• STMicroelectronics : STM32-F7 and H7 families
• NXP : Kinetis V Series, i.MX RT Series
• PJRC : Teensy 4 / 4.1

Development tools

Development board with Cortex-M3 type LPC1343 from NXP

As integrated development environments among others which is GNU toolchain with Eclipse available. There are also various commercial offers, for example from IAR or Keil. Real-time operating systems such as embOS, FreeRTOS , OpenRTOS, SafeRTOS or SCIOPTA can be used as operating systems. It is also possible to run µClinux on processors with an external memory interface . As a debugger for the JTAG interface include the GNU debugger available in conjunction with OpenOCD for the hardware connection.

The documentation is very extensive. In particular, the core functions of the Cortex-M family are described in the ARM documentation and are identical for all implementations. The various specific hardware implementations and manufacturer-specific extensions, however, are described in the respective manufacturer documents.

literature

• Joseph Yiu: The Definitive Guide to the ARM Cortex-M0 . 2nd Edition. Newnes, 2011, ISBN 978-0-12-385477-3 , pp. 552 .
• Joseph Yiu: The Definitive Guide to the ARM Cortex-M3 . 2nd Edition. Newnes, 2009, ISBN 978-1-85617-963-8 , pp. 479 .

Web links

• ARM Cortex-M website
• Quick Reference Cards for the instruction sets: Thumb (PDF; 127 kB), ARM and Thumb-2 (PDF; 226 kB), Vector Floating Point (PDF; 99 kB)

Cortex-M series	ARM website	ARM core	ARM architecture
M0	M0	Cortex ™ -M0 Revision: r0p0 - Technical Reference Manual (PDF; 472 kB)	ARMv6-M
M0 +	M0 +	Cortex-M0 + Revision: r0p1 Technical Reference Manual (PDF; 427 kB)	ARMv6-M
M1	M1	Cortex ™ -M1 Revision: r1p0 - Technical Reference Manual (PDF; 943 kB)	ARMv6-M
M3	M3	Cortex ™ -M3 Revision: r2p1 - Technical Reference Manual (PDF; 889 kB) Cortex ™ -M3 Revision: r1p1 - Technical Reference Manual (PDF; 2.1 MB)	ARMv7-M
M4	M4	Cortex®-M4 Revision: r0p1 - Technical Reference Manual (PDF; 813 kB) Cortex ™ -M4 Technical Reference Manual ARM DDI 0439B Errata 01 (PDF; 121 kB)	ARMv7E-M
M7	M7

Individual evidence

1. ↑ Cortex-M0, -M0 + and -M1 belong to the ARMv6 architecture and Cortex-M3 and -M4 to the ARMv7 architecture.
2. ↑ Cortex-M0 m0 r0p0 Technical Reference Manual; ARM Holdings. (PDF; 461 kB)
3. ↑ Cortex-M0 + m0p r0p0 Technical Reference Manual; ARM Holdings. (PDF; 417 kB)
4. ↑ Cortex-M1 m1 r1p0 Technical Reference Manual; ARM Holdings. (PDF; 943 kB)
5. ↑ ^{a b} Cortex-M3 m3 r2p0 Technical Reference Manual; ARM Holdings. (PDF; 2.4 MB)
6. ↑ ^{a b} Cortex-M4 m4 r0p1 Technical Reference Manual; ARM Holdings. (PDF; 914 kB)
7. ^ Cortex-M23. Retrieved March 2, 2018 . 
8. ^ Cortex-M33. Retrieved March 2, 2018 . 
9. ↑ ^{a b c d e f g h i j} ARMv6-M Architecture Reference Manual; ARM Holdings.
10. ↑ ^{a b c d e f g h i j k l} ARMv7-M Architecture Reference Manual; ARM Holdings.
11. ↑ ^{a b} ARMs Cortex-M7 - the key to security-critical applications? . Frank Riemenschneider, elektroniknet.de. Retrieved September 24, 2014.
12. ↑ ^{a b} ARMv8-M Architecture Reference Manual, Edition Ad Accessed on March 3, 2018 . 
13. ^ Cortex-M3 Embedded Software Development; App Note 179; ARM Holdings. (PDF; 179 kB)
14. ↑ ^{a b} ARM's mini-core is set to redefine the MCU market . Frank Riemenschneider, elektroniknet.de. Retrieved May 27, 2010.
15. ↑ ^{a b c} ARM introduces the smallest 32-bit core of all time . Frank Riemenschneider, elektroniknet.de. Retrieved March 13, 2013.
16. ↑ ARM Cortex-M3 Specifications , ARM Holdings, engl.
17. ^ ARM Information Center. Retrieved February 24, 2017 . 
18. ↑ ARM Cortex-M7 Devices Generic User Guide: 4.6.1. MPU Type Register. In: infocenter.arm.com. Retrieved September 30, 2016 . 
19. ↑ atmel.com
20. ↑ st.com
21. ↑ Kinetis® V Series: Real-time Motor Control & Power Conversion MCUs based on Arm® Cortex®-M0 + / M4 / M7 | NXP. Retrieved January 25, 2018 . 
22. ↑ segger.com RTOS.
23. ↑ sciopta.com RTOS; IEC61508.