PicoBlaze

As Picoblaze an exclusively is FPGAs and CPLDs the company Xilinx usable processor family called. The processors do not exist as physical hardware, but are available in the hardware description languages VHDL and Verilog as so-called soft cores , which makes it very easy to expand them by adding peripherals to small microcontrollers.

Due to the special optimization for the special features of certain FPGA / CPLD components from Xilinx, the logic requirement of the processors is very low. The disadvantage is that due to the optimization and legal restrictions PicoBlaze processors can and may only be used on FPGAs and CPLDs from Xilinx.

The strength of the PicoBlaze processors lies in their use as a finite state machine , although this should not be particularly time-critical. Implementation of finite state machines directly in the hardware description language are strongly size-dependent depending on the scope of the states, which can be avoided by using a PicoBlaze processor. This simplifies the development of the rest of the hardware. Due to the comparatively small scope of performance of PicoBlaze processors, other, more powerful processors or microcontrollers such as the MicroBlaze , also available from Xilinx for FPGAs as softcore, should be used for more complex tasks .

PicoBlaze processors were originally called KCPSM, which is an abbreviation for Constant (k) Coded Programmable State Machine . It is often assumed that KCPSM is an abbreviation for Ken Chapman's Programmable State Machine . Ken Chapman, the developer of the PicoBlaze processors at Xilinx, denies this with a wink.

PicoBlaze family

PicoBlaze 3

The PicoBlaze processor family includes the following derivatives:

PicoBlaze CPLD (optimized for Xilinx CoolRunner-II CPLDs)
PicoBlaze (optimized for Xilinx Virtex-E and Spartan-II / IIE FPGAs)
PicoBlaze II (optimized for Xilinx Virtex-II FPGAs)
PicoBlaze 3 (optimized for Xilinx Spartan-3 and newer Spartan, Virtex-II, Virtex-II Pro, Virtex 4 and newer Virtex FPGAs)
PicoBlaze 6 (optimized for Xilinx Spartan-6 and newer Spartan, Virtex-6 and newer Virtex FPGAs)

Hardware characteristics

PicoBlaze processors are based on an 8-bit RISC architecture. The speed varies greatly with the hardware used, but can reach well over 100 MIPS . Two clock cycles are required to execute an instruction.

feature	PicoBlaze	PicoBlaze II	PicoBlaze 3	PicoBlaze 6	PicoBlaze CPLD
Number of IO port addresses	256	256	256	256	256
Number of registers	16	32	16	2 × 16	8th
Scratchpad size [in bytes]	-	-	64	64/128/256	-
Call stack size	15th	31	31	30th	4th
Max. Program size [in commands]	256	1024	1024	1024/2048/4096	256

IO ports: PicoBlaze processors each have an 8-bit wide input and output port that can be addressed via 8-bit port IDs, which theoretically results in 256 input and output ports. In practice, however, the actually possible number of port addresses is limited by the signal delay resulting from the wiring and the clock frequency used.
register: The PicoBlaze processors have different numbers of 8-bit registers . The registers are functionally identical and can be used with all register commands. The PicoBlaze 6 has two register banks, each containing 16 registers.
Scratchpad: The scratchpad is a RAM memory in which register values can be stored or read back using the STORE and FETCH commands. In some cases, the scratchpad size can be set using parameters.
Call stack: The call stack of all PicoBlaze processors is used jointly for both CALL calls and interrupts .

Instruction set

The PicoBlaze has a small command set that is limited to the most important commands.

command	PicoBlaze	PicoBlaze II	PicoBlaze 3	PicoBlaze 6	PicoBlaze CPLD
Program flow
JUMP	Yes	Yes	Yes	Yes	Yes
CALL	Yes	Yes	Yes	Yes	Yes
RET	Yes	Yes	Yes	Yes	Yes
Interrupt
RETI	Yes	Yes	Yes	Yes	Yes
UNITE	Yes	Yes	Yes	Yes	Yes
DINT	Yes	Yes	Yes	Yes	Yes
logic
AND	Yes	Yes	Yes	Yes	Yes
OR	Yes	Yes	Yes	Yes	Yes
XOR	Yes	Yes	Yes	Yes	Yes
COMP	No	No	Yes	Yes	No
COMPC	No	No	No	Yes	No
TEST	No	No	Yes	Yes	No
TESTC	No	No	No	Yes	No
arithmetic
ADD	Yes	Yes	Yes	Yes	Yes
ADDC	Yes	Yes	Yes	yes ¹	Yes
SUB	Yes	Yes	Yes	Yes	Yes
SUBC	Yes	Yes	Yes	yes ¹	Yes

command	PicoBlaze	PicoBlaze II	PicoBlaze 3	PicoBlaze 6	PicoBlaze CPLD
Shift and rotate commands
SR0	Yes	Yes	Yes	Yes	Yes
SR1	Yes	Yes	Yes	Yes	Yes
SRX	Yes	Yes	Yes	Yes	Yes
SRA	Yes	Yes	Yes	Yes	Yes
RR	Yes	Yes	Yes	Yes	Yes
SL0	Yes	Yes	Yes	Yes	Yes
SL1	Yes	Yes	Yes	Yes	Yes
SLX	Yes	Yes	Yes	Yes	Yes
SLA	Yes	Yes	Yes	Yes	Yes
RL	Yes	Yes	Yes	Yes	Yes
I / O, move data
REGBANK	No	No	No	Yes	No
LOAD	Yes	Yes	Yes	Yes	Yes
LOADRET	No	No	No	Yes	No
IN	Yes	Yes	Yes	Yes	Yes
OUT	Yes	Yes	Yes	Yes	Yes
FETCH	No	No	Yes	Yes	No
STORE	No	No	Yes	Yes	No
STAR	No	No	No	Yes	No
NOP	Yes	Yes	Yes	Yes	Yes

¹ The implementation of the command differs from the previous processors with regard to the zero flag.

For further details on the commands, the application notes can be consulted (see web links).

programming

Because of their simplicity, the PicoBlaze processors are practically exclusively programmed in assembler . Given that they Xilinx DOS - compiler are, different were from the Community Integrated Development Environments produced which provide both editors and compilers and simulators are available.

PicoBlaze processors are usually not programmed directly like conventional processors or microcontrollers, since access to the program memory from outside the FPGA / CPLD is only possible to a limited extent. Instead, a pre-initialized VHDL / Verilog program memory instance is generated with one of the numerous compilers, which can be integrated into your own circuit together with the processor instance. The compilers use a VHDL / Verilog template for this, which is read in and supplemented. It is thus possible to influence the program memory type, which enables the use of dual-port memory blocks as program memory.

When using dual-port memory blocks as program memory, two PicoBlaze processors can optionally work with the same memory / program or the program memory can be changed during runtime using additional logic.

Troubleshooting

Since access to the internal processor hardware in the FPGA / CPLD is not possible, PicoBlaze processors cannot be diagnosed directly at runtime like conventional processors or microcontrollers. PicoBlaze processors are usually seamlessly integrated into their own VHDL / Verilog code, which is why this fact does not mean a loss, since the entire code (VHDL / Verilog, PicoBlaze program) should generally be diagnosed with a VHDL / Verilog simulator, because a malfunction of the FPGA / CPLD can be caused by the VHDL / Verilog as well as the processor code.

Various PicoBlaze simulators are available for an abstract view of the processor code.

Individual evidence

↑ http://forums.xilinx.com/xlnx/board/message?board.id=PicoBlaze&message.id=61

Web links

Xilinx links

Community links

[1] ttp://forums.xilinx.com/xlnx/board/message?board.id=PicoBlaze&message.id=61