Altera Nios
NIOS is the product name of an embedded processor from the chip manufacturer Altera in the form of a so-called soft core processor . With this a synthetic CPU that can be implemented in an FPGA or ASIC .
application
The current processor version is fully called Nios II and has been up-to-date since 2005 - using the original first version is not recommended.
In practice, the Nios is an extensive collection of design instructions in the form of files, which define the functions of electrical circuits in a hardware description language. These designs can of special HDL - compilers read and translated to a circuit configuration as in a programmable logic device is written. This module then contains the fully functional processor.
Altera supports hardware-software co-design by offering different versions of Nios that differ in hardware architecture but are software compatible . This makes it possible, for example, to choose between a faster or a more compact design. In addition, the processor can be configured with additional modules, such as a floating point unit , in order to optimize the performance for a specific task.
Together with other, application-specific circuit parts such as RAM or IO interfaces, which are usually implemented on the same chip, this processor then acts as specific hardware and can be loaded and operated with software (e.g. in C or C ++ ) like a normal processor . In this way, existing systems that were originally purely hardware-based can easily be expanded and existing software can be reused.
The NIOS system is put together using the SOPC builder (System-On-a-Programmable-Chip). A SOPC project consists of individual logic blocks that form sinks or sources for data. The individual logic blocks are connected to one another using an Avalon switch fabric . The SOPC Builder offers a graphical user interface to describe the target system graphically. The configured system consisting of processor and hardware is then exported to a set of VHDL or Verilog files. B. an FPGA from Altera can be configured as a system on a chip . In addition, the FPGA code obtained in this way can be used to generate ASICs.
Matura
The maturity and certification level of the Nios CPU is now also suitable for the implementation of safety-critical applications.