Field programmable gate array

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A Field Programmable Gate Array ( FPGA ) or programmable logic gate is an integrated circuit (IC) of digital technology into which a logic circuit can be loaded. The English term can be translated as a (logic) gate arrangement that can be programmed in the field (i.e. on site, at the customer's premises) .

In contrast to the programming of computers , microcontrollers or controls, the term programming here refers not only to the specification of time sequences, but above all to the definition of the desired circuit structure. This is formulated using a hardware description language and translated into a configuration file by the generation software, which specifies how the physical elements in the FPGA are to be interconnected. One therefore speaks of the configuration of the FPGA. Without this, the block has no function.

FPGAs represent a further development of PLDs and are used in many areas of digital electronics.

An FPGA from Altera


Various circuits and functions can be implemented in an FPGA by configuring the internal elements. These range from low complexity circuits such as B. a simple synchronous counter or interfaces for digital components, up to highly complex circuits such as memory controllers and complete microprocessors .

FPGAs are used in all areas of digital technology, but especially where fast signal processing and flexible changes to the circuit are important, for example to be able to make subsequent improvements to the implemented functions without having to change the hardware directly. A large area of ​​application is the creation of prototypes in the ASIC development for the previous test as well as the maintenance area, which is about keeping electronics for old, no longer available digital components or microcontrollers.

With the introduction of the FPGAs, compact, user-specific circuits were made possible in small numbers. Today they allow the cost-effective and flexible production of complex systems such as mobile - base stations as an alternative to more expensive contract manufacturing by semiconductor manufacturers.

In addition to the FPGAs, there are also FPAAs (Field Programmable Analog Array) that contain not only digital, but above all analog function blocks that can be programmed and interconnected by the user. These are primarily filters and RF components .

Structure and structure

Logic block of an FPGA with 4-bit LUT and optional output flip-flop
Switching matrix as a connection structure between logic blocks

The fundamental structure of an FPGA is an array of basic blocks, each with a simple programmable lookup table (LUT) and a 1-bit register ( flip-flop ). The LUTs can implement any n-digit binary function, depending on the number of available inputs . The desired function is programmed by storing the defining truth table in the SRAM cells of the LUT, and the function is calculated by reading out the memory address determined by the inputs. For a long time, LUT structures with 4 binary inputs were common. Newer FPGAs are changing over to LUTs with up to 6 inputs to reduce the cost of LUT-to-LUT connections for implementing functions with more inputs.

In addition to the LUTs, the interconnection of the components on the FPGA can also be configured with a large degree of freedom. Multiplexer structures in the basic blocks often enable very fast local signal paths to integrate or bypass the flip-flop, to feedback from its output, to connect neighboring blocks and the like. For the more distant connections, there is a grid of immense bus structures between the basic blocks, to which inputs and outputs can be connected. Further programmable switching components in the intersection points of the grid allow the signal to be distributed over the entire chip.

Other components

Further, often found elements of FPGA are:

  • Input / output blocks ( IO blocks or IOB ) are used for communication with the outside world. They are used to connect the connections of the FPGA to the switching matrix. These blocks can also be adapted to the respective application, e.g. B. the output voltage can be adapted to the respective standard ( TTL / CMOS etc.).
  • On the basis of the clocks made available at the inputs, one or more clock generators generate all the internal clocks required for the application. These can be shifted in phase with respect to the input clocks and have a frequency derived from the respective input clock. Clock amplifiers and a corresponding interconnection ensure that every clock used is available synchronously everywhere in the chip. Modern FPGAs typically have one or more phase-locked loops (PLL) with which rationally broken clock divisions / multipliers can be generated. Delay-locked loops (DLL) and digital frequency synthesizers (DFS), which some FPGA manufacturers prefer to PLL, serve the same purpose .
  • Complex FPGAs contain additional hard-wired functions such as: B. memory blocks (so-called. Block RAM ), which can be used in a variety of ways.
  • For digital signal processing tasks such as digital filters , some FPGAs also contain multiplying units. These allow two binary numbers to be multiplied particularly quickly without the need for logic cells.
  • FPGAs, which are used in the field of system-on-a-chip (SoC), have a number of mostly complex hard cores to accommodate a complete system. Hard cores are fixed and unchangeable circuits of mostly complex function blocks, such as microcontrollers or Ethernet interfaces . Complex hard cores occupy much less chip area than the same function, implemented with logic blocks, would require and are typically three to four times faster than the freely configurable logic of the FPGA. However, these circuit parts are not so flexible and their function can no longer be changed.

Manufacturers such as Xilinx now also offer SRAM- based FPGAs that already have flash memory housed in the chip housing for configuration and no longer require external flash memory. Such integrated circuits with several chips in one housing are also called multi-die . The loading and starting times of the FPGA remain roughly the same compared to external memory, but have been specially optimized by the manufacturer. Another advantage is the protection against unauthorized copies by reading out the external memory. At present and for the foreseeable future, it is technologically not possible to replace the SRAM-based switch cells in an FPGA directly with Flash or EEPROM cells, as is the case with the much simpler CPLDs .

Differences to CPLDs

FPGAs are often equated or compared with the digital and also reconfigurable CPLD modules (Complex Programmable Logic Devices). The main differences between FPGAs and CPLDs are:

  • CPLD still belongs to the group of PAL (Programmable Array Logic) / PLA (Programmable Logic Array) / PLD (Programmable Logic Device) / GAL (Generic Array Logic), but has a more complicated internal structure in the IC than PAL and GAL. The even newer FPGAs, however, belong to a different technology. Compared to FPGAs, CPLDs have a much simpler structure. They do not have a fine-meshed array (field) of logic blocks and flip-flops, but only a configurable switching matrix that can connect different input signals to different output signals. The signals can be linked by logical operations such as AND / OR . This means that CPLDs have a constant signal transit time that is independent of the respective design. With appropriate design methods, a defined maximum throughput time can also be achieved with FPGAs ( timing constraints ).
  • CPLDs have comparatively few flip-flops. In particular, longer shift registers, counters, state memories and similar circuits that require many flip-flops can only be implemented inefficiently in CPLDs.
  • Since each IO pin has a flip-flop, CPLDs usually have a large number of IO pins that are only partially used in many applications. In applications in which only comparatively simple digital circuits, so-called glue logic , with a high need for IO pins are used, CPLDs are usually the better choice.
  • Due to their simple structure, CPLDs can work with flash cells in the switching matrices. This means that a CPLD is ready for operation immediately after being switched on (power-up), while reconfigurable FPGAs with SRAM-based cells first have to go through a charging cycle for configuration. Some manufacturers have also been offering FPGAs in flash technology for a long time. Since the late 1990s, CPLDs have been moving closer to FPGA-SRAM technology. Today most CPLDs work internally based on SRAM. In some CPLD families, the basic logic element now consists of the LUT4 flip-flop combination typical of FPGAs (Altera MAX II series).
  • Due to their simpler structure and smaller size, CPLDs also have significantly lower power consumption.


The programming of the logic elements can be solved differently depending on the FPGA. A distinction can be made between methods that allow the FPGA to be programmed several times and methods that only allow one-time programming. With FPGAs that can be programmed several times, the configuration is stored in memory cells (e.g. SRAM , EPROM , EEPROM , Flash ). With the one-time programmable FPGAs, the physical properties of the connection paths are permanently changed ( antifuse technology ). This technology offers greater security against external interference in the field.

The LUTs and the connection structures in SRAM-based FPGAs are typically configured once before each use, which means that the FPGA is set to a specific function. This is necessary because the FPGA loses its configuration again when the operating voltage is switched off. In use, the FPGA is therefore usually supported by a kind of EPROM that holds the configuration and the content of which can also be updated . The FPGA can load itself from this non-volatile memory. Alternatively, the configuration can also be done actively by a microcontroller or another FPGA that writes the configuration to the FPGA.

As a rule, the FPGA then retains its function until it is switched off. However, more and more area-by-area reprogramming of individual FPGA areas is supported during operation in order to use the space in the FPGA more effectively and to make hardwired functions more flexible.

The process of configuring the FPGA is often referred to as programming, but this involves a conceptual overlap with the design.

Design steps and tools

Xilinx FPGA

Programming is often used when developing FPGA circuits . In this context, however, the term is to be understood differently than it is known from the creation of software for processors. As part of the development process, a circuit design is first carried out, followed by a check of the resulting hardware description using simulation tools and then an implementation ( place and route ) and, if necessary, runtime-based simulation. Only then can the implemented circuit be tested on the real FPGA.

Circuit design

The configuration of a FPGA either graphically by means of a created wiring diagram (engl. Schematic ) or textually with a hardware description language . These are primarily VHDL or Verilog , which describe the entire function of the circuit in the form of structures and processes. A so-called synthesis tool executes this description like a program and then creates a specific network list for a desired module in several steps using the resources available in this module.

The sequence controls required in the FPGA can in turn be represented by finite automatons . The hardware-describing code is then generated automatically in an intermediate step. In addition, graphic programming systems such as LabVIEW or Matlab / Simulink or the free Logiflash can also be used to automatically create circuit modules for an FPGA.

In the last few years several projects tried to describe hardware implementations for ASICs , FPGAs and CPLDs with the programming language C (HardwareC, HandelC, BachC). Current approaches are based directly on the widely used standard languages ​​ANSI C or C ++ or Python (with MyHDL ). There are no synthesis tools for SystemC , the practical use for concrete FPGA developments lies in the abstract behavior modeling and significantly accelerated system simulations, which is why it has become the widespread industry standard there. There are also high-level synthesis tools for generating a draft at register transfer level ( VHDL , Verilog ) from high-level languages ​​(C / C ++, MATLAB, Java , Python , UML ) . Examples are Catapult C Synthesis from Mentor Graphics , CoDeveloper from Impulse Accelerated Technologies , Cynthesizer from Forte Design Systems or the free MyHDL mentioned above.

Manufacturer-specific languages ​​such as Altera-HDL (AHDL) or the rarely used hardware description language ABEL were used as well as UDL / I (Japan).

For the integration of embedded systems in FPGAs there are tools that offer a construction at the function block level, e.g. B. Xilinx EDK (Embedded Development Kit). Function blocks such as FIFOs , processors, serial interfaces, Ethernet MAC layers, RAM controllers, parallel IO etc. are provided by the manufacturer. These functional units, called IP cores , are sometimes available as source code or usually as an encrypted network list and can usually be parameterized (e.g. baud rate for serial asynchronous interfaces or FIFO depth or width of the parallel interface). These are connected to other functional units via buses.

Timing simulation of a digital circuit


After the description during the design flow, further steps such as functional simulation and synthesis follow . A well-known tool for simulation is ModelSim® .

For FPGAs, a synchronous circuit design is recommended when designing the circuit, although not absolutely necessary. This means: At all flip-flops in a so-called clock domain (Engl. Clock domain ), the same clock. The data transfer to an FPGA flip-flop is best controlled only via the additional clock enable inputs and not via shared clock signals ( gated clocks ). This avoids runtime effects that are difficult to manage. Some FPGAs offer special switches that guarantee interference-free ( glitch-free ) switching between different clock sources during operation.

Implementation and test

Based on a verified logic circuit, the network list for the specific FPGA is then implemented, with external function blocks that are offered by third-party providers and previously only existed as black boxes being inserted. Subcircuits intended for testing the FPGA, such as integrated logic analyzers, can also be added in this step.

Using further boundary conditions, the conversion to a programming file for loading the FPGA takes place, from which a further programming file can be generated, which is used to load the flash memory.

Application examples

Since their beginnings, FPGAs have increasingly expanded their area of ​​application from the classic " glue logic ", i.e. the pure connection logic between different digital components, and are now used even in medium quantities for the implementation of complex digital circuits through to complete digital systems. The fact that FPGAs can be reconfigured directly by the end user also has the major advantage of being able to react to current technical developments and being able to adapt the digital circuits through updates without having to change the underlying hardware of the FPGA chips directly.

FPGAs are used, for example, for real-time processing of simple to complex algorithms, for digital signal processing in the context of digital filters or for fast Fourier transformation . However, protocol implementations such as parts of the Ethernet MAC layer, the coding of digital video signals, the encryption of data and error correction methods are also areas of application.

The use of reconfigurable FPGAs instead of ASICs is particularly appropriate in areas in which algorithms or protocols are subject to rapid further development. The advantages are quick market readiness, the possibility of subsequent bug fixes, adaptation to new developments.

For some classes of computing problems, FPGA-based parallel computers are also very suitable. Probably the best-known example are FPGA computers for breaking cryptographic procedures, such as the Data Encryption Standard (DES). The parallel computer COPACOBANA , which consists of 120 FPGAs, is such a parallel computer for code breaking.

The number of logic blocks that can now be achieved allows the integration of several embedded computer systems in a single FPGA component including CPU (s), bus system (s), RAM, ROM, RAM controller, peripheral controller, etc. Such complete systems are called system-on -a-Chip (SoC). Due to their reconfigurability, the SRAM- and Flash-based FPGAs form the basis for reconfigurable computers .

Digital storage oscilloscopes are often implemented with FPGAs, as their quantities are usually too small to design an ASIC for this application. Fast digital storage oscilloscopes use several A / D converters in parallel per channel , which scan the signal to be measured out of phase. This requires a very high degree of parallel data processing and storage, for which FPGAs are well suited. FPGA-based oscilloscopes can, for example, trigger on very short pulses below the sampling rate of the A / D converter or count them. Another advantage of using FPGAs is that, unlike DSPs, relatively low development costs arise for new designs if one of the ICs used is no longer available and its function can be integrated into an existing module.

FPGAs are very often used as a development platform for the digital part of ASICs in order to verify the function. This is necessary because, due to the complexity of today's circuits, simulations alone would be too time-consuming.

Many publications from various application areas report on the migration of an application from software to Configware with acceleration factors of one to four orders of magnitude. That is why FPGAs are used in reconfigurable computing and in the replacement of microcontrollers.

A daughter card standard specially tailored to FPGAs is the FPGA mezzanine card .


FPGAs developed in the mid-1980s as a separate sub-area of semiconductor components . The circuit combination of programmable read-only memory (PROM) and programmable logic circuits ( English programmable logic device, PLD ) can be viewed as a precursor to FPGAs . David Westminster Page and LuVerne R. Peterson patented the combination of reprogrammable memory elements for the realization of logical links in the form of an "array" on a semiconductor chip, but was not implemented commercially.

The first commercially available FPGA was the XC2064 device , which was developed by Ross Freeman and Bernard Vonderschmitt, both founders of the Xilinx company , in 1985. The XC2064 consisted of 64 configurable logic blocks, so-called Configurable Logic Blocks (CLBs), with a lookup table (LUT) with three inputs. The logic blocks were arranged in an 8 × 8 matrix (array) and could be contacted via switchable connecting lines. In 2009, Freeman was inducted into the US National Inventors Hall of Fame for developing the first FPGA .



Depending on the configuration, FPGAs represent any arrangement of digital circuit functions and thus basically offer the possibility of processing information completely in parallel. In this way, the resulting data flows can be optimally adapted to one another in terms of bandwidth and information depth. Signals that are to be detected quickly are often processed fully in parallel with copies of identical circuit blocks, signals that occur more slowly are processed more and more cyclically with a single circuit and thus save space.

External processors, on the other hand, can process very complex and nested programs sequentially with little hardware. In the case of an FPGA, a separate piece of hardware would have to be synthesized for each operation, the limited number of logic gates having a limiting effect, and the construction of a comparably flexible structure is extremely difficult and time-consuming. Therefore, for more complex tasks, a so-called soft core CPU is used, which is integrated into the FPGA design. This is similar to the external CPUs and provides a standardized structure that is programmed in the classic way in C. Today's FPGAs are sometimes so powerful that you can integrate a large number of 8, 16 or 32-bit CPU cores. However, depending on the configuration, more complex CPU cores require a lot of logic resources, which, in addition to the costs, is reflected in the relatively low processing power compared to standard processors. This is why there are now FPGAs that contain one or more hardware-based CPU cores. After initial attempts with ARM -9 (Altera) and PowerPC 405 (Xilinx), the trend since 2010 has been towards ARM-Cortex architecture. SoC-FPGAs with dual-core Cortex-A9 and permanently integrated peripherals have established themselves at Altera and Xilinx. In the high-end class, Xilinx offers the UltraScale family of components that contain two CPU clusters (QuadCore Cortex-A53 and DualCore Cortex-R5). Microsemi, on the other hand, integrates the simpler Cortex-M3 architecture into its SmartFusion family.

In contrast to FPGAs, single-core processors are purely finite state machines that have to get by with a fixed hardware and process their program sequentially, which also results in significant differences in the design of the implementation of algorithms. Microprocessors often have a fixed periphery. That is both an advantage and a disadvantage. On the one hand, the periphery does not have to be generated separately, but it can be adapted to the problem in an FPGA.

Modern processors with SIMD instructions such as the Intel i7-3930K process up to 96 floating point instructions in parallel (48 additions + 48 multiplications), the achievable throughput is 3.2 GHz with theoretically around 300 GFlops, of which 250 GFlops are used for practical tasks are attainable. Current FPGAs can carry out tens of thousands of fixed point additions (up to 48 bits) and thousands of fixed point multiplications (up to 18 × 25 bits) at clock frequencies of 500 MHz at the same time. For processing tasks that can be processed with fixed-point arithmetic, this enables processing power to be increased by a factor of 2 to 3 with significantly lower power consumption.

Advantages and disadvantages compared to ASICs


  • Significantly lower development costs (in contrast to ASICs, masks with very high fixed costs are not required)
  • very inexpensive for prototypes and small series
  • Shorter implementation times
  • Easily correctable and expandable (reconfigurable)
  • Less design risk because it doesn't have to be ready long before the hardware ships
  • flexible IO ports and standards, d. H. adaptable to technical changes in the environment


  • Higher unit price from medium quantities (than ASICs)
  • Lower clock rates (currently available up to 1.5 GHz, typically 20–500 MHz are implemented; digital ASICs offer> 3 GHz)
  • Lower logic density (approx. 10 times the space required compared to ASIC of the same technology)
  • Reduced possible complexity of the programmable logic
  • Significantly higher power requirements for the same amount of logic or functions
  • Higher sensitivity to particle radiation and electromagnetic waves (as programmed via RAM cells and not through hard wiring)
  • Less flexibility, what equipment z. B. concerns with embedded memory or analog elements, but also with IO buffers
  • The shorter design cycle and the possibility of correcting errors at a very late stage tempt you to conduct less functional tests in advance.
  • SRAM -based FPGAs (these are all offered by the market leaders Xilinx and Altera , for example ) must be reloaded every time the power is interrupted. This means that the functionality is not available immediately after switching on. Loading can take up to a few seconds, depending on the technology used. If it is not a matter of special FPGAs with integrated flash memory, additional, external components are necessary, e.g. B. a manufacturer-specific EEPROM or flash memory that contains the configuration or a microcontroller with additional flash memory that carries out the loading process.

FPGA manufacturer

  • Xilinx - FPGA producer since 1984 - market leader, offers the most extensive SOPC system
  • Intel PSG (formerly: Altera ) - provider of a migration path from FPGA to structured ASICs
  • Lattice - provider of a free 32 bit open source SoftCore processor and GAL technology. Has bought SiliconBlue (energy-saving FPGAs of the iCE family)
  • Microchip (formerly: Atmel & Actel or Microsemi) - FPGAs, also with additionally integrated RAM and AVR microcontroller
  • NanoXplore - Radiation Resistant FPGAs
  • QuickLogic - since 1988 - supplier of energy-saving FPGAs
  • Aeroflex - Radiation Resistant FPGAs
  • Achronix Semiconductor - Very fast FPGAs (up to 1.5 GHz) in 22 nm
  • Abound Logic - Power-saving FPGAs with high logic density
  • GOWIN Semiconductor - FPGAs with a small number of logic blocks, non-volatile and SRAM-based, SoC with Bluetooth


  • Rajeev Murgai et al. a .: Logic Synthesis for Field-Programmable Gate Arrays. Springer, 2012, ISBN 978-1-4613-5994-4 .
  • Zoran Salcic et al. a .: Digital Systems Design and Prototyping Using Field Programmable Logic. Springer, 1997/2013, ISBN 978-1-4613-7807-5 .
  • Uwe Meyer-Baese: Digital Signal Processing with Field Programmable Gate Arrays (Signals and Communication Technology). 4th Edition, 2014, Springer, ISBN 978-3-642-45308-3 .
  • Esteban Tlelo Cuautle et al. a .: Engineering Applications Of Fpgas (Chaotic Systems, Artificial Neural Networks, Random Number Gener ...). Springer, 2016, ISBN 978-3-319-34113-2 .

Web links

Commons : Field-programmable gate arrays  - collection of images, videos and audio files

Individual evidence

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  9. Patent US4524430 : Dynamic data re-programmable PLA. Published June 18, 1985 , Inventor: David W. Page.
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  12. Lattice Semiconductor Acquires Chipmaker SiliconBlue For $ 62 Million In Cash. In: TechCrunch . December 9, 2011, accessed April 11, 2019 .