Glitch (electronics)
In electronics , glitch [ glɪtʃ ] denotes a brief false statement in logical circuits and temporary falsification of a Boolean function . This occurs because the signal propagation times in the individual gates are never completely the same. This falsification is therefore also referred to as a race condition . The susceptibility to glitches increases with the complexity, the increase in speed and the reduction in size of the circuits, but can also be present in very simple circuits. They represent a major problem in the development of modern electronic circuits and fast microprocessors , but this was also the case with the older electromechanical relay technology .
A glitch is sometimes also referred to as a hazard or a spike .
example
Explanation of the switching symbols → see: Logic gate # Types of logic gates and symbols
Graphic 1  the circuit
Consider a circuit that has three inputs: x _{0} , x _{1} and x _{2} . It should return the value "1" if at least one of the two conditions is met:
If at least one of the two conditions does not apply, it should output "0". 

Situation 1  The circuit delivers a 1 as required
The circuit is now in situation 1. According to our specifications, the first condition is met, namely x _{1} and x _{0} are “1”. The branches that carry the information "1" are shown in red. The inverter converts the incoming "1" into a "0". Therefore, the following AND element no longer lets a signal through, so it outputs a "0". The entire circuit (OR element) still delivers a "1", since the other AND element delivers the "1". 

Situation 2  Inverter causes a glitch
In situation 2, x _{1} = 0 and x _{2} = 1. The circuit should continue to output a "1". However, the inverter needs a certain amount of time to perceive the conversion of the x _{1} signal from "0" to a "1". For a short time both x _{1} = 0 and (x _{1} ) '= 0. This circumstance is processed as if none of the conditions is met and consequently outputs a "0". This situation is known as a glitch . 

Situation 3  The circuit outputs the correct value again
After some time  on the order of nanoseconds  the circuit is in situation 3: the inverter has processed the new information. The now output "1" runs into the AND gate, which (again after a short delay) then also delivers a "1". The entire circuit now delivers the desired "1". 
Distinctions
Function and structure glitches
Functional hazards arise from the simultaneous change in occupancy of more than one variable. These hazards can be avoided by changing the assignment ( Gray coding ), by clocking or by a delay (RC element at the output).
Structural hazards arise in circuits with more than one level by changing from one block in the KV diagram (= gate in the circuit) to an adjacent block (no overlapping blocks in the KV diagram). These hazards can be avoided by implementing redundant prime conjunctions (overlapping blocks in the KV diagram) or by clocking.
According to this nomenclature, the example given above is a structural hazard.
Static and dynamic glitches
There are two types of glitches: static and dynamic . A glitch is static when there is no change in the output value, but the glitch briefly supplies the other value. A dynamic glitch , on the other hand, jumps back briefly to the old one after a change to the new value.
Depending on whether the glitch occurs when changing to a 1 or a 0, a distinction is still made between 0glitches and 1glitches .
Meaning of glitches
In practice, runtime differences also exist in gates of the same type or in lines of different lengths. If you want to know the exact value of the function, you have to wait a corresponding time until all glitches have been eliminated. This fact significantly limits the clock frequency of modern processors .
Elimination
The Karnaugh diagrams are an important aid for designing switching functions . In principle, it is also possible to implement larger circuits without glitches. However, this requires additional components in the circuit, and even with somewhat more complex structures, their number is enormous, which makes the circuit more expensive. A good compromise has to be found between the cost of the circuit and the duration of the glitches.
Avoid the Impact
D flip flops
The effects of glitches can be prevented in synchronous circuit designs by downstream Dflipflops . The idea is that the outputs of the combinational circuit parts, consisting of various gates with different running times, only have to assume valid states when the clock edge accepts the output values in the D flipflops. In the time between two clock edges, any number of glitches can occur in the combinatorial part due to delay effects, since these intermediate states are not taken into account by the downstream D flipflop. The disadvantage is that the smallest time unit is the clock period of the D flipflop and there is no longer an output signal that is continuous in time as in a purely combinational circuit.
The process of always providing the outputs of combinational circuit parts with D flipflops is one of the essential principles for stable, digital circuit designs in complex, freely programmable FPGAs .
Alignment of the delay times
In the example above, this procedure could consist in inserting another (functionless) gate in the upper branch of the line going out from input x1 so that the signal change reaches the two AND gates at the same time. However, this method is fraught with uncertainties and does not reliably deliver the desired result.
Systematic approach
The better method is the systematic approach. To do this, the KV diagram on which the circuit in question is based is optimized . The diagram for the example above shows two blocks that are implemented by the two AND gates ( disjunctive normal form ). The hazard arises at the transition between these two blocks. The hazard is resolved if this transition is bridged with another block, which is logically superfluous, and which overlaps with both blocks: x _{0} and x _{2} are simultaneously “1”. A further AND gate must then be inserted accordingly in the resulting circuit. The circuit can then no longer be fully tested statically, since a faulty AND gate is not noticed. The hazard can not be measured with today's gate times .
It should be noted, however, that not only different transit times of individual gates can have an effect in the form of glitches, but also the different transit times of the signals in the connecting lines. To do this, the individual connecting lines must be modeled with the aid of line theory . These transit times are not taken into account in the systematic resolution using KV diagrams. This method can therefore only be used with comparatively low switching frequencies (= quasistationary case) or discrete circuit parts that are operated with appropriately matched connecting lines. At high signal rates, where 100 MHz can be used as a rough guide, and if the developer can only have little influence on the specific signal routing (e.g. when interconnecting within FPGAs ), even resolved combinational circuits do not deliver glitchfree Designs.