Gate runtime

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As a gate delay time (engl. Propagation delay ) is referred to in the digital and electrical engineering , the components used for the ( gate characteristic) runtime of signals from an input to an output of the gate. This time is abbreviated with t P or t PD , or depending on the direction, with t PLH for rising edges or t PHL for falling edges at the output.

Gates as discrete components have run times in the range of a few nanoseconds (ns) to over 100 ns, see logic family . The times are specified by the manufacturers in the data sheets for certain conditions, usually for a capacitive load corresponding to the fan-out and a high temperature , sometimes separately for different supply voltages . Usually three values ​​are given each, minimum value, typical value and maximum value. The limits are guarantees from the manufacturer. They are generously dimensioned, as the manufacturers measure at most random samples.

Transit times are measured precisely using the frequency of a ring oscillator . The times vary within one and sometimes differ significantly from batch to batch and between manufacturers.

Within integrated circuits, gates are designed for lower voltages and currents, the inputs have a lower capacitance because there is no protective circuit. Therefore the gate delay times are much smaller. For FPGAs that can be configured at the gate level , they are in the range of a few 10 to 100  picoseconds , and within processor cores they are sometimes well below a picosecond.

In addition to gate delay times, there are also delay times on signal paths. The so-called runtime tolerance calculation provides specific methods for determining total runtimes through any network . Failure to observe the gate delay times can result in timing violations and glitches in the circuit.