Register transfer level

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The register transfer level ( English register transfer level , RTL ) is a level of abstraction in the hardware modeling of integrated circuits . When designing at this level, the system is specified by the flow of signals between the registers .

The RTL is used in hardware description languages such as VHDL and Verilog to generate high-level representations of circuits. From these representations on lower levels and finally the concrete hardware can be synthesized.

With software tools, the RTL description can be translated into a network list , from which a physical layout is finally generated through placement and routing .

The synthesis that a logic circuit generates from an RTL model is called RTL synthesis .

literature

  • Peter Marwedel: Embedded System Design . Springer, Dordrecht 2006, p. 81, ISBN 0-387-29237-3 .