Very High Speed ​​Integrated Circuit Hardware Description Language

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Very High Speed ​​Integrated Circuit Hardware Description Language (also VHSIC Hardware Description Language ), VHDL for short , is a hardware description language with which it is possible to describe digital systems in a text-based manner. VHDL has been defined as the IEEE standard since 1987 and there are now some standardized language extensions. In addition, there are voice derivatives such as VHDL-AMS, which can also be used to describe analog or mixed-signal systems.

As a description language, VHDL is not a programming language; However, since it describes objects whose task is mostly information processing, data processing can still take place via their simulation by processing "input data" provided for this simulation run by the (simulated) hardware into "result data". This detour enables VHDL (in combination with a simulator) to describe Turing-complete data processing like a programming language .
With advanced circuit generators it is sometimes even possible to specify only the algorithm itself instead of the hardware structure for an algorithm; the associated circuit is generated fully automatically. VHDL brings this closer to a programming language.


VHDL was created as part of the VHSIC initiative, which was set up by the US government in 1980 to make up for a technology deficit in the development of Very High Speed ​​Integrated Circuits compared to the private sector . The language definition was the product of standardization efforts by a committee in which most of the larger CAD providers and CAD users, but also associations such as the IEEE , were represented. As a major North American customer has then US Department of Defense (Engl. Department of Defense ) VHDL made to prevail. It demanded that all ASICs developed on their behalf after September 30, 1988 must be documented in VHDL. However, it was only required that realistic descriptions of behavior should be created in VHDL. The implementation language - be it VHDL, VerilogHDL or the graphic input that was customary up to that point - remained open to the contractors. The aim was to standardize at least the circuit documentation and to enable the simulation of complex digital system descriptions from various sources. The first commercial version was released in 1985. It was the result of a collaboration between IBM , Texas Instruments and Intermetrics .

VHDL is standardized by the IEEE 1076 standard from 1993. Compared to the first standard from 1987 (IEEE 1076-1987), the language has been expanded, but some constructs of the old syntax have also been removed and the semantics of constructs have been changed in a few individual cases .

An extension of the description to the analog area of ​​electrical systems was achieved with AHDL . Efforts are currently being made to create a general language for describing technical systems - see VHDL-AMS (VHDL analog / mixed signal). This should leave the framework of purely electronic circuits and also model mechanical elements, sensors and actuators in order to be able to capture these in a system simulation .

Current EDA tools currently support the version VHDL-2002 and VHDL-2008.


VHDL does not work with individual electronic components, but describes the desired behavior of a circuit on a higher level of abstraction. VHDL enables large and complex circuits (e.g. microprocessor with over 20 million transistors) that require high efficiency (in terms of time and economy) to be developed quickly and supports the developer in all work.

In this way a system can be simulated, synthesized and finally a netlist can be created. A verification is possible both through full simulation and formally .

The network list can be used to produce masks for the production of MPGAs ( mask programmable gate array ) or similar LSI ( large scale integration ) chips or it can (after conversion to a suitable bitstream ) directly into an FPGA ( field programmable gate array ) or CPLD ( Complex Programmable Logic Device ) must be loaded.

In addition to VHDL, there are Verilog and ABEL . The most widely used hardware description languages ​​worldwide are VHDL and Verilog.

VHDL has developed into the "quasi-standard" in Europe, while Verilog is the most widely used language in the USA.

Synthesisable and functional VHDL code

It is necessary to distinguish between synthesizable and functional code, because there are constructs that can be simulated, but cannot be translated into real hardware and thus into a network list . What is actually synthesizable VHDL code from the wide range of functional VHDL code is primarily determined by the translation program ( synthesis tool ) selected for VHDL synthesis . Functional code that cannot be synthesized is primarily used in the area of circuit simulation and to create so-called test benches, sometimes also to check new methods such as the behavior of interface protocols in advance.

Producing synthesis-capable VHDL code is usually more complex and the developer has to consciously forego large parts of the language options of VHDL and know the target hardware and its exact properties better. For example, VHDL code for input and output via the operating system ( textio ), such as writing and reading files or outputting texts on the screen, cannot be synthesized.

Simulation and verification of VHDL code

In the meantime, VHDL has established itself as the standard for simulation models of Intellectual Property (IP). The VHDL code or VHDL module that is actually to be tested and capable of synthesis is embedded in a simulation model and the hardware is therefore reproduced as faithfully as possible in a so-called 'test bench'. The simulation model is mostly written in VHDL that cannot be synthesized, which allows the time behavior or certain physical parameters of the external circuit parts to be modeled.

An example should explain this process:

  • When creating an SDRAM controller, a circuit for controlling SDRAM memory modules, the SDRAM with its memory and its behavior over time are simulated as precisely as possible in the simulation model, just like the real SDRAM hardware. In this way, the controller can be simulated in its logical function and the behavior under extreme temporal conditions can be verified without the need for real hardware. If necessary, the SDRAM controller is functionally improved accordingly in order to meet the simulation boundary conditions. The SDRAM controller created in this way is only put into operation on hardware, for example in an FPGA , in combination with 'real' SDRAM modules when this simulation is successful . This means that the development process for IP cores is largely independent of specific hardware.

The creation of good test benches that allow corresponding statements is a task that is mostly underestimated and accounts for around 50% of the total development time for IP cores. In addition to a systematic approach to development, it is much more efficient than going to real hardware at an early stage with circuit parts that usually do not work immediately - all of their parameters can then be verified with difficulty and with great effort.

A further distinction is made between different types of simulation in the simulation:

  • A pure behavioral simulation of the IP core to be implemented. The functional relationships in the circuit are always checked. For example, whether logical links between individual signals are suitable. The advantage lies in the low computational effort, with which longer sections can be simulated.
  • A simulation of the fully placed IP core ( post-fit simulation ). The IP core is first synthesized, routed and placed, then the network list and the associated runtime information of the target hardware are determined from the completed circuit arrangement. The application of the runtime parameters to the VHDL code ( back annotation ) is either taken over by appropriate tools, which generate non-synthesizable VHDL code from them, or it is done directly in the simulation program. The advantage lies in the more precise model, for example, in order to be able to recognize timing problems in the target hardware in the simulation. Disadvantages are the high computational effort involved and the very long simulation times, even on fast computers, which can vary in the range of a few days depending on the complexity of the circuit.

A further distinction can be made between test benches with their own error detection and test benches that only represent the pure time course. In the first case, the tests to be performed are determined in the test bench based on fixed decisions (“test vectors”) and automatically determined by corresponding text output. The creation of such test benches is more complex, but offers the advantage of being able to check the implementation changes completely and reliably in the event of later changes ( regression test ). In the second case, the circuit to be simulated is only shown in terms of its time behavior ( wave diagram ) without an automatic evaluation of the output being carried out. The decision as to whether the behavior of the circuit is correct is up to the person who has to check this time behavior manually. The advantage of this method is the simplicity in creating the testbenches, which is why it is mainly used for simple circuits. A disadvantage is that errors in the implementation can easily be overlooked by manual testing, especially with complex circuits. Another disadvantage is that a manual check has to be carried out again after each change to the VHDL code.

Skeleton of a VHDL module

      ENTITY Bausteinname IS
      GENERIC (Parameterliste, optional);
              - dieses Statement erlaubt die Übergabe modellabhängiger
                Parameter (z. B.: Verzögerungszeiten) an einem Baustein;
      PORT (Schnittstellenliste, optional);
              - hier werden die Signalschnittstellen des Bausteins nach außen
                definiert; folgende Modi sind möglich IN, OUT, INOUT, BUFFER;
              - an dieser Stelle können diverse Deklarationen vorgenommen werden,
                die in verschiedenen Architekturrümpfen benutzt werden können,
                das sind unter anderem Unterprogramme, Typendeklarationen,
                Konstantendeklarationen und Signaldeklarationen;
      BEGIN (Anweisungen, optional);
              - hier können Anweisungen stehen, die für alle Architekturrümpfe
                durchzuführen sind; das verkürzt die Architekturbeschreibung,
                denn in Bausteindeklarationen aufgeführte Anweisungen müssen
                nicht mehr in den Architekturrümpfen stehen;
      END Bausteinname;
              - Ende der Bausteindeklaration

Architectural hull:

      ARCHITECTURE Rumpfname OF Bausteinname IS
         - an dieser Stelle können optional diverse Deklarationen für
           Typen, Konstanten und Signale vorgenommen werden,
           im Gegensatz zu den Bausteindeklarationen sind diese hier
           nur für den vorliegenden Architekturrumpf gültig;
         - Anweisungen, die das Verhalten oder die Struktur des
           Bausteins beschreiben;
      END Rumpfname;

Programming styles

The programming styles used in the architecture body can be reduced to a few basic forms in the area of ​​synthesizable VHDL. Sometimes the use of certain VHDL styles is also specified in certain development projects:

  1. The Dataflow style, which is particularly popular among hardware developers and beginners . It is characteristic that a large number of parallel and mostly small and synchronous processes and concurrent instructions are used per architecture that are connected to one another via signals. With the processes, individual, mostly elementary hardware structure elements are mapped directly in VHDL and the signals are used both for status storage within the individual processes and for information transfer between these processes. While this style is still manageable with small architectures , the confusion of the program code becomes a disadvantage with larger models. Due to the parallelism of the individual processes and their interactions, it is difficult to understand the behavior of the entire circuit.
  2. The so-called 2-process method. With this VHDL style, which is particularly advantageous in the synchronous FPGA design, the architecture consists of only two processes: a mostly very complex, purely combinatorial process, which contains the complete algorithm and the procedure, and a very simple clocked process, which contains all registers (State memory). By combining individual signals in records , even complex algorithms can be clearly described. By mapping the procedure in only one combinatorial process, the concurrency of several processes , which is difficult to understand with the dataflow style, can be avoided and, similar to a programming language with variables, described with a sequential process. The debugging of the VHDL code can also take place due to the sequential processing within the one combinatorial process using methods similar to those used in software development.

Differences and similarities to classic programming languages

The structure of a physical circuit is described as a model in a hardware description language. No algorithms are described, but hardware that can calculate an algorithm. Only in the component simulation, with "applied input data / signals", does (simulated) data processing take place, which is comparable to the execution of a program in a classic programming language.

In most programming languages, parallel processes can be described; similarly, VHDL can describe hardware modules that exist and work simultaneously.

In VHDL one differentiates

  • Entities ('entity') that describe templates for circuit blocks and their inputs and outputs, and
  • Components ('component') that represent instances of these templates (cf. class and object in object-oriented programming languages), and
  • Processes that summarize parallel instructions.

In VHDL, data can be of different types, which often reproduce real circuit states, but also calculation variables such as integers . There are signals , variables and constants for processing .

  • Signals are used as inputs and outputs and also for data transmission between concurrent processes in the same component. In a clocked circuit, a signal is also used to store values. In the case of a synthesis, it is modeled as a register.
  • Variables are used within processes and are used there to provide a clear structure and simplify the code. If a variable (seen sequentially) is read in a clocked process before it is written, a register is implicitly created during the synthesis.
  • Physically, constants represent hard wiring; in simulation, they are synonymous with constants in conventional programming languages.

The functional difference between signals and variables is that signals only assume their new state at the end of a sequential process, while variables behave similarly to programming languages ​​and assignments have an immediate effect. This fact is mostly confusing, especially for beginners, but becomes clear as soon as it has been internalized that a process is not a sequential sequence of commands, but everything happens simultaneously .

VHDL for analog circuits, VHDL-AMS

Since 1999, various efforts have been made within the framework of the IEEE to use VHDL for the simulation and, in the future, also for the synthesis of analog and mixed analog-digital circuits. The designation for this extended language is VHDL-AMS and it is defined in the IEEE 1076.1-1999 standard.

As part of VHDL-AMS, for example, analog temperature sensors can be modeled with their electrical signal behavior as a function of the temperature at the connection terminals. It is also possible to model differential equations in VHDL-AMS to describe electrical network elements such as coils or capacitors .

Until 2006, no synthesis tools for circuits described in VHDL-AMS were available. Various commercial software packages such as Saber from Synopsys, AdvanceMS from Mentor Graphics or SMASH from Dolphin Integration were already available on the market for circuit simulation . These simulation programs are to be seen in addition to established analog circuit simulation programs of the SPICE class (Eldo, Specter, hSpice etc.). They enable the joint simulation of behavior models together with circuits at component level (Spice). This is a basic requirement for the top-down method in circuit design. Since VHDL-AMS represents a superset of VHDL, the simulation together with purely digital circuit parts is also possible in VHDL.

VHDL editors

  • HDL-Designer is a commercial graphical input tool for VHDL and Verilog .
  • Crimson Editor for Windows
  • DataFlow : graphical input under UNIX
  • zamiaCAD : open source plugin for Eclipse
  • Signs : Plugin for Eclipse
  • Sigasi : Eclipse-based editor for VHDL and Verilog under Windows x86 / x64, Linux x86 / x64, Mac

There are also additional packages for VHDL support for many common text editors , for example for vi , Notepad ++ and Emacs .

Common VHDL simulators also have their own VHDL editor with text highlighting and the like. This not only enables the code to be entered, but also helps with troubleshooting thanks to its integration, since, for example, codes can be jumped to from the compiler / simulator / ... from error messages and breakpoints can be implemented in the source text.

VHDL simulators

  • ModelSim from Mentor Graphics , for Windows, Linux and Unix
  • ActiveHDL from Aldec , for Windows
  • RivieraPro from Aldec, for Windows and Linux
  • Portunus from Adapted Solutions, for Windows
  • SimPlorer from Ansoft, for Windows
  • SMASH from Dolphin Integration, for Windows, Linux and Unix
  • ISE Simulator (ISim) from Xilinx , also in free ISE WebPACK, for Windows and Linux
  • Quartus II from Altera , also a free Web Edition, for Windows and Linux
  • GHDL , open source , for Windows, Linux and Apple OS X
  • SystemVision from Mentor Graphics, for Windows
  • NCSim from Cadence Design Systems , for SunOS and Linux


  • Jürgen Reichardt, Bernd Schwarz: VHDL synthesis, design of digital circuits and systems . 7th edition. De Gruyter Oldenbourg, Berlin 2015, ISBN 978-3-11-037505-3 .
  • Paul Molitor, Jörg Ritter: VHDL - An Introduction. Pearson studies, Munich 2004, ISBN 3-8273-7047-7 .
  • Gunther Lehmann, Bernhard Wunder, Manfred Selz: Circuit design with VHDL , Franzis-Verlag, Poing 1994, ISBN 3-7723-6163-3 , free download ( Memento from June 11, 2010 in the Internet Archive )
  • Peter J. Ashenden: The Designer's Guide to VHDL. Morgan Kaufmann Publishers, San Francisco 2002, ISBN 1-55860-674-2 .
  • Peter J. Ashenden: VHDL - 2008. Just the new stuff. (Systems on Silicon) . Morgan Kaufmann Publishers, San Francisco 2008, ISBN 978-0-12-374249-0 .
  • Yannick Herve: VHDL-AMS . Oldenbourg, Munich 2006, ISBN 3-486-57787-5 .
  • VASCO - RTL VHDL Application on Synthesis . MABEX - Multimedia Limited, Zielona Góra 1999, ISBN 83-907288-9-3 .
  • Frank Kesel, Ruben Bartholomä: Design of digital circuits and systems with HDLs and FPGAs: Introduction with VHDL and SystemC . Oldenbourg, Munich 2006, ISBN 3-486-57556-2 .

Web links

Wikibooks: VHDL tutorial  - learning and teaching materials
Commons : VHDL  - collection of images, videos and audio files

Individual evidence

  1. VHSIC Program Office: Very High Speed Integrated Circuits - VHSIC - Final Program Report 1980-1990 , 1990. September 30, site of the Defense Technical Information Center . Retrieved January 15, 2011.
  2. 2-process method (English; PDF; 33 kB)
  3. Emacs VHDL Mode developer site at ETH Zurich
  4. GHDL website