Advanced Boolean Equation Language

The Advanced Boolean Equation Language ( ABEL ) is a hardware description language that is rarely used today , which was used in digital technology in the 1980s and 1990s to create simple logic circuits for components such as CPLDs ( Complex Programmable Logic Devices ) and for smaller FPGAs ( Field Programmable Gate Array ). The description is done with Boolean equations, truth tables or conditional assignments. With state machines, the state transitions can be described as STATE_DIAGRAM. While Verilog and VHDL were originally only designed for circuit simulation, the focus in the design of ABEL was on the automatic and very hardware-oriented generation of programming files for CPLDs.

ABEL was developed in the 1980s by the "Data I / O Corporation" in Redmond (Washington). After a number of sales, ABEL has been maintained by Xilinx since 1999 . Today, ABEL is only rarely used, as more abstract descriptions, such as in VHDL, can be automatically converted into tag lists with the advent of powerful synthesis tools. For circuits that consist of several hundreds of thousands of logic gates, the manual description with logic equations as in ABEL is not practical. But ABEL is hardly used for smaller circuits either, since the complete functionality can be covered with today's hardware languages such as VHDL or Verilog.

ABEL syntax

Program structure

An Abel program consists of different sections, which are introduced by appropriate key words (e.g. module, declarations, equations, truth_table, state_diagram, test_vectors). A maximum of 150 characters are allowed per line. All lines end with a semicolon.

Reserved keywords

There are about 30 keywords that cannot be used freely (e.g. if, else, istype, buffer, com, when, then, truth_table, equations, etc.)

Identifier (self-defined signal identifier)

Identifiers must begin with a letter or an underscore and can be up to 31 characters long. Identifiers may not contain any special characters (except ~ and _), umlauts (ä, ö, ü) or spaces. Identifiers are case-sensitive !

Comments

There are two ways to mark comments.

Start and end with " mark
Start with // - applies up to the end of the line, useful if the comment itself contains "

Constants (selection)

.X. don't care condition (e.g. in section truth_table)
.C. complete cycle: low-high-low (e.g. in test_vectors)
.K. full clock high-low-high
.D. descending clock edge
.U. rising clock edge

Operators

There are 4 groups of operators in ABEL: logical operators, arithmetic operators, relational operators and assignment operators.

Logical operators are :! (NOT), & (AND), # (OR), $ (XOR) ,! $ (XNOR), << (Shift left) and >> (Shift right)
Arithmetic operators are + (addition), - (subtraction or two's complement), * (multiplication) and / (division)
The comparison operations correspond to the syntax of many high-level languages. Possible are == , ! = , < , <= , > , <=

In the case of assignments, a distinction is made between combinatorial assignments and assignments with memory:

= for outputs without flip-flop (and for outputs with FF using dot extensions)
: = for outputs with flip-flop

Dot extensions of a D flip-flop in a CPLD

Dot extensions

DOT extensions in ABEL are an important aid for accessing internal signals of the D flip-flops contained in the CLPD. The illustration shows the most frequently used dot extensions:

.OE switches the tristate buffer
.D is the data input of the flip-flop
.CLK designates the clock input of the flip-flop
.AR denotes the asynchronous reset input of the flip-flop

.Q is the output of the flip-flop. Only .Q can be used with internal flip-flops (NODE) .

.Pin is the signal at the output pin . By using .OE , bidirectional buses are also possible.

Further dot extensions are implemented directly or emulated for specific modules. In a CPLD that only contains D flip-flops, the behavior of a JK or RS flip-flop can be simulated using .J and .K or .R and .S . If the internal flip-flops of the CPLD do not have an asynchronous set signal ( .AS ), the logic of the flip-flop is inverted when using .AS and the asynchronous reset input .AR is used instead . It can .AR and .AS not be used simultaneously.

Example of traffic light switching in ABEL-HDL

The following source code represents a program for simple traffic light switching, which runs through the traffic light phases red - red / yellow - green - yellow - red - etc. as long as a high signal is present at the enable input.

MODULE trafficlight
TITLE 'trafficlight'
DECLARATIONS
// inputs
    clk    pin 11; // clock signal
    en     pin  9; // enable signal to start the traffic light
// nodes
    q0     node   istype 'reg';
    q1     node   istype 'reg';
// output
    red    pin 36 istype 'com'; // the red light
    yellow pin 42 istype 'com'; // the yellow light
    green  pin 39 istype 'com'; // the green light
EQUATIONS
    q0 := !q0 & !en;
    q1 := (q1 $ q0) & !en;
    q0.clk = clk;
    q1.clk = clk;
    red = q1;
    yellow = !q0;
    green = !(q1 & !q0);
TEST_VECTORS
           ([clk, en] -> [ red, yellow, green]);
@repeat 1  {[.C., 1] -> [.X., .X., .X.];}
@repeat 7  {[.C., 0] -> [.X., .X., .X.];}
@repeat 3  {[.C., 1] -> [.X., .X., .X.];}
@repeat 40 {[.C., 0] -> [.X., .X., .X.];}
END

Web links

University of Pennsylvania's ABEL primer ( February 7, 2005 memento in the Internet Archive )
Xilinx ABEL Reference Guide

Individual evidence

↑ XILINX Completes Purchase Of Software Assets . ( Memento of April 23, 2000 in the Internet Archive ) Press release

[1] XILINX Completes Purchase Of Software Assets . ( Memento of April 23, 2000 in the Internet Archive ) Press release