RISC-V
RISC-V (official pronunciation: "risc-five") is an open instruction set architecture (ISA) that is based on the design principle of the Reduced Instruction Set Computer . Unlike most instruction set architectures, RISC-V is not patented and, thanks to the permissive BSD license, can be used freely. Everyone is allowed to design, manufacture and sell RISC-V microprocessors. A large number of companies offer or have announced RISC-V hardware.
RISC-V has properties that increase computer speed but still reduce costs and energy consumption. This includes a load store architecture, bit patterns to simplify the multiplexers in a CPU, simplified standard-based floating point numbers, a design that is architecture neutral, and setting the most significant bit in a fixed position to expedite sign expansion. Sign extension is considered to be often on the critical path. The instruction set was designed for a variety of applications. It has a variable width and is expandable so that more coding bits can be added at any time. It supports three word sizes: 32, 64 and 128 bits and a choice of subcommand sets. The definitions of each subcommand set vary slightly from the three word widths. The sub instruction sets support compact embedded systems , personal computers , high-performance computers with vector processors and arithmetic center compatible, in 19-inch frame built parallel computers .
The instruction set space for the instruction set expanded to 128 bits was reserved because 60 years of industry experience has shown that most irreparable errors in the design of instruction sets are caused by a lack of memory address space. In 2016, the 128-bit part of the instruction set was intentionally undefined, as there is little experience with such large storage systems. There are proposals to implement instructions with a variable width of up to 864 bits.
The project began in 2010 at the University of California, Berkeley under the direction of Krste Asanovic and David A. Patterson and is already being developed and funded by hardware and software developers worldwide. Unlike other academic designs, which are usually optimized for ease of explanation, the RISC-V instruction set was designed for practical use in computers.
Version 2.2 of the userspace ISA and version 1.11 of the privileged ISA have been defined since June 2019 and enable software and hardware manufacturers to use or implement this. A debug specification is available as a preliminary draft version 0.3.
Awards
- 2017: The Linley Group's Analyst's Choice Award for Best Technology (for the instruction set)
Manufacturer of the corresponding chips
See also
Web links
Individual evidence
- ^ RISC-V ISA - RISC-V Foundation . In: RISC-V Foundation . (American English, riscv.org [accessed February 3, 2018]).
- ↑ FAQ - RISC-V Foundation . In: RISC-V Foundation . (American English, riscv.org [accessed February 3, 2018]).
- ^ Wolf, Clifford: Alternative proposal for instruction length encoding. Retrieved October 20, 2019 .
- ^ Contributors - RISC-V Foundation . In: RISC-V Foundation . ( riscv.org [accessed February 3, 2018]). Contributors - RISC-V Foundation ( Memento of the original from June 13, 2018 in the Internet Archive ) Info: The archive link has been inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice.
- ^ RISC-V International: Privileged ISA Specification. Retrieved June 9, 2019 .
- ^ The Linley Group Announces Winners of Annual Analysts' Choice Awards . January 12, 2017 ( linleygroup.com [accessed January 21, 2018]).
