SystemVerilog

SystemVerilog is a hardware description and verification language ( English Hardware Description and Verification Language , or HDVL for short). It offers possibilities for the design and verification of digital circuits. SystemVerilog was developed by Accellera and is an extension of the IEEE 1364-2001 Verilog HDL. SystemVerilog works on a higher level of abstraction than Verilog-2001.

history

Verilog-1995 has been on the market for many years and, along with VHDL, is the most widely used hardware description language. The IEEE has expanded the properties of Verilog-1995; these were classified in Verilog-2001. However, this scope of language is still insufficient for a powerful verification of the digital hardware described in Register Transfer Level (RTL). Therefore the developers often used other languages ​​such as " e ", Vera or Testbuilder . Since SystemVerilog is both a hardware description language and a verification language, both parts of the language must be considered separately. The hardware description aspect of SystemVerilog is a consistent evolution of the Verilog 2001 standard. The situation is different with the verification aspect of SystemVerilog. This part of the language was significantly influenced by Synopsys Vera, so its object-oriented syntax clearly stands out from Verilog-2001.

SystemVerilog was standardized in several stages. SystemVerilog 3.0 was released in June 2002, Version 3.1 in May 2003 and finally Version 3.1a in April 2004. With the development of SystemVerilog 3.1, the most important verification techniques should be integrated into SystemVerilog. SystemVerilog has been maintained as the IEEE Standard 1800 since 2005. In 2009 the standard was expanded and that of IEEE 1364 was incorporated into it. In 2013 the next, rather minor revision was published under the designation IEEE 1800-2012.

General information about SystemVerilog

Some of the features of SystemVerilog:

• Data types analogous to 'C': int, typedef, struct, union, enum
• Dynamic data types: struct, classes, "dynamic queues", "dynamic arrays"
• New operators and "built-in methods"
• Extended program control: foreach, return, break, continue
• Semaphores, mailboxes and " events "
• Object-oriented programming classes
• " Assertions "
• Code coverage analysis
• VPI extensions ( Verilog Procedural Interface )

The IEEE has standardized SystemVerilog as IEEE Standard 1800. Anyone with C ++ experience will quickly become familiar with SystemVerilog. Since SystemVerilog is very similar to C ++, someone who has never dealt with object-oriented programming will find it difficult to use SystemVerilog to its full extent.

SystemVerilog consists of three parts: the well-known and standardized Verilog, a second part, which defines the writing of assertions in SystemVerilog, and the object-oriented part, which is used exclusively for verification.

functionality

Example of the use of character strings and screen output

// Dies ist ein SystemVerilog-Kommentar.
string sv = "SystemVerilog";
string s;
s = {sv, " ", "ist echt einfach."};
$display ("%s\n", s); // Bildschirmausgabe: "SystemVerilog ist echt einfach."
s = {s, " - probiert es mal!"};
$display ("%s\n", s); // Bildschirmausgabe: "SystemVerilog ist echt einfach. - probiert es mal!"

See also

• SystemC

Web links

• http://www.systemverilog.org/
• http://www.asic-world.com/systemverilog
• http://www.doulos.com/knowhow/sysverilog/
• http://www.project-veripage.com/
• http://electrosofts.com/systemverilog/ SystemVerilog tutorial

Individual evidence

1. ↑ P1800-2009 IEEE Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language. IEEE, Piscataway, New Jersey 2009, ISBN 978-0-7381-6129-7 .
2. ↑ 1800-2012 - IEEE Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language. Institute of Electrical and Electronics Engineers , accessed November 24, 2014 . 
3. ↑ Stuart Sutherland: Keeping Up with Chip - the Proposed SystemVerilog 2012 Standard Makes Verifying Ever-increasing Design Complexity More Efficient (PDF; 82 kB).