SystemC

SystemC is a modeling and simulation language especially for the development of complex electronic systems that include both hardware and software components.

In contrast to pure hardware description languages such as VHDL and Verilog-HDL , SystemC is not a separate programming language, but a C ++ class library. It is defined in the current IEEE standard 1666-2011. In addition, an open source implementation of the standard is available under the Apache 2.0 license . As a class library, SystemC C ++ extends language elements that are used for hardware modeling. At the same time, the library has a simulator core so that models described with SystemC can be executed and tested.

SystemC is primarily used for modeling on higher levels of abstraction, e.g. B. used for Transaction Level Modeling (TLM) . SystemC is therefore particularly suitable for electronic system level designs , where the early provision of a virtual prototype for the evaluation of design alternatives is of great importance. Classic RTL designs would be too complex and inflexible here.

Another advantage of SystemC is not only the rapid development of prototypes, but also the significantly improved simulation performance on higher abstraction levels. Models designed in SystemC at the transition level can have a simulation performance that is around a thousand times faster than RTL models. This means that more complex programs can also be simulated and design alternatives with regard to the partitioning of hardware and software components can be weighed up. But also the modeling of synthesizable circuits on register transfer level is possible with SystemC as a substitute for VHDL or Verilog.

Since SystemC is not an independent language, but a pure ( class ) library for C ++, all typical language elements of conventional hardware description languages must be mapped to simple C ++ language constructs. This brings SystemC the disadvantage of a syntactic overhead that conventional hardware description languages do not have. Providing a variety of preprocessor - Macros helps mitigate this effect somewhat. The developer is much more free to express himself, but this usually conflicts with the ability to synthesize the hardware model.

SystemC is suitable, such as B. also the modeling language E , for the modeling of protocols and peripherals, in order to use this to check the faultlessness of a digital circuit. SystemC is not just a modeling language, but also its own simulation core. This is contained in the SystemC library (e.g. in every reference implementation of the OSCI), so that an executable simulator with the behavior of the source code is created by compiling a system source code. However, SystemC is also supported by commercial simulation tools such as Modelsim .

Many universities are working on efficient programs for circuit synthesis from SystemC models. Some companies offer solutions that can generate net lists for ASICs or FPGAs from certain SystemC codes . In 2005, version 2.1 of the SystemC reference description was ratified by the international engineering association IEEE as the IEEE 1666-2005 standard, which was replaced by 1666-2011 in 2012. This standard represents the current LRM (Language Reference Manual) and is available as a free download from the IEEE (see web links). In 2007, the open source reference implementation of the OSCI (Open SystemC Initiative) was updated to version 2.2 to be fully compliant with the IEEE 1666 LRM.

In 2016, the Analog Mixed Signal Extension SystemC AMS was ratified as a standard (IEEE 1666.1-2016). An open source reference implementation is available as a free download (see web links).

syntax

Since SystemC is a class library for C ++, only the constructs typical for SystemC are given here.

Modules

Modules serve to break down more complex systems into manageable parts. They form building blocks, are externally accessible via ports and can in turn contain modules. The syntax is

SC_MODULE (Modulname) {
// Modulinhalt
};

An instance of the module is created by the constructor

SC_CTOR (Modulname) {. . . }

realized.

Signals and ports

Ports form the interface between the module and the outside world. There are three types of ports and, as a fourth type, signals:

sc_in<Porttyp> PortInName; // Eingang
sc_out<Porttyp> PortOutName; // Ausgang
sc_inout<Porttyp> PortInOutName; // Bidirektional
sc_signal<Signaltyp> SigName; // Signal

Processes

The functionality of the modules is formed by processes. There are three types of processes.

Method processes are called when a signal from the sensitivity list changes and after they have been executed, control is passed back to the simulator. By

SC_METHOD (Funktionsname);

a certain function is installed that has to be declared in the module beforehand. The sensitivity list is through

sensitive << Signal1 << Signal2 . . .

generated.

In contrast to method processes, thread processes are only started once and run through the same loop over and over again, in which wait () commands are used to temporarily interrupt.

SC_THREAD (Funktionsname);

Clocked thread processes are synchronous thread processes whose actions are only visible on the next clock edge . In contrast to the thread processes, there is no specification of the sensitivity list, but the second argument in the call

SC_CTHREAD (Funktionsname, Taktflanke);

specifies which edge of the clock signal triggers the process.

example

An adder in SystemC:

#include "systemc.h"

SC_MODULE(adder) {        // Moduldeklaration (eine Art Klasse)
  sc_in<int> a, b;        // Zwei Eingangs-Ports (a und b)
  sc_out<int> sum;        // Ein Ausgangs-Port

  SC_CTOR(adder) {
    SC_THREAD(doit);
    sensitive <<a <<b;
  }

  void doit() {
    while(true) {
      sum.write(a.read() + b.read());
      wait();
    }
  }
};

literature

Frank Kesel, modeling of digital systems with SystemC. From RTL to transaction level modeling . 2012. ISBN 978-3-486-70581-2

Web links

Website development group of SystemC (English)
SystemC standard IEEE 1666-2005 (English)
SystemC standard IEEE 1666-2011 (English)
SystemC AMS standard IEEE 1666.1-2016 (English)
SystemC AMS Proof-of-Concept Download (English)
Fraunhofer IIS / EAS SystemC-AMS Homepage (English)
European SystemC Users Group (English)
SCLive, a Linux LiveCD with a complete SystemC simulation environment (English)
Doulos Guide to SystemC (English)
Use of SystemC in hardware / software codesign , diploma thesis (PDF; 532 kB)
Veripool SystemC utilites and Verilog to SystemC compiler (English)
2 diploma theses on the topic of simulator coupling using SystemC

Individual evidence

↑ SystemC. Retrieved February 8, 2019 .
^ G. Martin: SystemC: from language to applications, from tools to methodologies . In: 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. September 2003, p. 3– , doi : 10.1109 / SBCCI.2003.1232796 ( ieee.org [accessed February 8, 2019]).
^ Frank Kesel: Modeling of digital systems with SystemC, from RTL to transaction level modeling . De Gruyter, Berlin, Boston 2012, ISBN 978-3-486-70581-2 , pp. 17 , doi : 10.1524 / 9783486718959 ( degruyter.com [accessed February 8, 2019]).

[1] SystemC. Retrieved February 8, 2019 .

[2] G. Martin: SystemC: from language to applications, from tools to methodologies . In: 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. September 2003, p. 3– , doi : 10.1109 / SBCCI.2003.1232796 ( ieee.org [accessed February 8, 2019]).

[3] Frank Kesel: Modeling of digital systems with SystemC, from RTL to transaction level modeling . De Gruyter, Berlin, Boston 2012, ISBN 978-3-486-70581-2 , pp. 17 , doi : 10.1524 / 9783486718959 ( degruyter.com [accessed February 8, 2019]).