OpenRISC

OpenRISC is a project of the OpenCores developer community . The goal of the project is to develop a highly configurable RISC - CPU as Open Hardware . The only completed architecture so far is the OpenRISC-1000 family (OR1k for short), which is available as a 32- and 64- bit version. The design of the OpenRISC 1200 (OR1200 for short) was the first to be published in the Verilog hardware description language under the GNU Lesser General Public License (GNU LGPL). The firmware and the microcode for the processor were made available under the GNU General Public License (GNU GPL). Based on the OpenRISC 1200 , a system-on-a-chip variant called ORPSoC (= OpenRISC Reference Platform System-on-Chip ) was developed. The operation of a Linux system was successfully tested on both variants . For this purpose, the processors were implemented in an FPGA .

construction

Block diagram of an OpenRISC-1200 processor

The design of the OpenRISC 1000 corresponds to a lean implementation of modern RISC architectures with 16 or 32 registers and a fixed instruction length of 32 bits. The 32 and 64 bit versions use the same instruction set . The design includes all the functions expected from today's desktop or server processors. These include, for example: virtual memory management , a secure virtual machine , MAC , a SIMD implementation or multi-processor system operation. The cache size can be scaled between 1 and 64 KiB .

Applications

Block diagram of the CPU / DSP of an OpenRISC-1200 processor

Most applications have so far been implemented on an FPGA. At the beginning of 2011, OpenCores issued an appeal for donations to produce an OpenRISC 1200 in ASIC technology for the first time . Although the OpenRISC-1000 design is considered stable, the performance and energy consumption are currently being optimized, which is why no ASIC chip has been produced until today (September 2012).

In addition to OpenCores' efforts to make a completely free chip, there are commercial implementations. Some companies used the OpenRISC-1200 or ORPSoC design as the basis for their own developments. The following processors were developed on the basis of OpenRISC 1000 :

• BA12, BA14, BA22 from Beyond Semiconductor are based directly on the OpenRISC 1200 .
• The OpenRISC 1200 is a functional unit on more complex ASIC from Flextronics International and Jennic Limited .
• Samsung uses ORPSoC in the chip series: SDP83 B, SDP92 C, SDP1001 / SDP1002 D, and SDP1103 / SDP1106 E. These chips are used as CPUs in DTV devices.
• Cadence Design Systems uses OpenRISC as a reference implementation in their documentation.
• On July 21, 2012 NASA launched a satellite called TechEdSat with an on- board computer based on OpenRISC 1200 .

Academic utilization

Since all details are known at OpenRISC due to the open source approach, the architecture is well suited for training, research and hobby developers. The following non-commercial applications are therefore known:

• A team at the Institute for Integrated Systems at the Technical University of Munich is researching the architecture and programming of multiprocessor systems on the basis of OpenRISC.
• The British Open Source Hardware User Group organizes events in which FPGA programming is learned or deepened using OpenRISC.

Operating systems and toolchain

In addition to Linux, RTEMS , FreeRTOS and eCos can run on the OpenRISC 1000 architecture. The port called or32 was included in the main development branch with version 3.1 of the Linux kernel and is therefore considered stable. A µClinux port is also available, but is currently not being further developed. In addition to the GNU toolchain , newlib , uClibc and Busybox have also been ported for OpenRISC 1000 . A port of LLVM is under development.

Emulators

The OpenRISC project provides an instruction set simulator, which is based on SystemC and directly accesses the processor sources available in the Verilog hardware description language. The following virtual machines can emulate an OpenRISC-1000 system:

• QEMU
• OVPsim
• jor1k (implementation in JavaScript )

Web links

• Official website

Individual evidence

1. ↑ OpenRISC 1000 Architecture Manual (English), Damjan Lampret et al., Rev. 1.3, November 15, 2007
2. ↑ Basic Custom OpenRISC System Hardware Tutorial: Embedded system design based upon Soft- and Hardcore FPGA’s ( Memento of the original from November 27, 2006 in the Internet Archive ) Info: The archive link was inserted automatically and not yet checked. Please check the original and archive link according to the instructions and then remove this notice. (PDF; 350 kB), (English), Patrick Pelgrims, Tom Tierens and Dries Driessens, De Nayer Instituut, Hogeschool voor Wetenschap & Kunst, 2004 
3. ↑ Open source embedded platform based on OpenRISC and DE2-70 (English), Xiang Li and Lin Zuo, KTH
4. ↑ OpenCores donation FAQ (English), OpenCores
5. ↑ OpenCores - Call for OpenRISC ASIC donations ( Memento of the original from May 1, 2011 in the Internet Archive ) Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. (English), OpenCores 
6. ↑ Samsung Open Source Release Center (search for OpenRISC)
7. ↑ UVM Reference Flow (English), Accellera.
8. ↑ NEWSLETTER SEPTEMBER 2010 ( Memento of the original from February 28, 2017 in the Internet Archive ) Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. (English) OpenCores, accessed September 7, 2012 
9. ↑ Multicore Architecture and Programming Model Co-Optimization (MAPCO) (PDF; 4.0 MB), Stefan Wallentowitz, Thomas Wild and Andreas Herkersdorf, Technical University of Munich, accessed: September 7, 2012
10. ↑ Chips (Programmable Logic, Computer Conservation with FPGAs, OpenCores & OpenRISC 1000) , OSHUG, accessed September 7, 2012
11. ↑ Practical System-on-Chip (Program your own open source FPGA SoC) , OSHUG, accessed September 7, 2012
12. ↑ Linux (English), OpenCores, accessed September 7, 2012
13. ↑ OpenRISC1200 platform ( Memento of the original from September 17, 2012 in the Internet Archive ) Info: The archive link was automatically inserted and not yet checked. Please check the original and archive link according to the instructions and then remove this notice. , OpenCores, accessed September 7, 2012 
14. ↑ project wiki page ( Memento of the original from October 14, 2013 in the Internet Archive ) Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. , OpenCores 
15. ↑ Qemu 1.2.0 improves Live Migration , Heise Zeitschriften Verlag, accessed September 7, 2012
16. ↑ jor1k project page