Gate array

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Gate array ULA from a Sinclair ZX81

Gate arrays are application-specific integrated circuits (ASIC) consisting of pre-assembled logic circuits that are linked in a customer-specific manner during final production. Gate arrays are alternatively referred to as master slice arrays , logic arrays , universal logic arrays or uncommitted logic arrays (ULA), see article .

The basic structure is a line-like arrangement of NOR or NAND logic gates (called master slice arrangement). The production of this matrix is ​​initially independent of the customer; the position of the logic gates, I / O lines, etc. is standardized. The customer-specific adaptations are limited to the internal wiring of the logic circuits, which is also carried out by the manufacturer on the basis of the draft supplied by the customer. But not all gate arrays are logical circuits, because gate arrays can also contain other circuits such as isolation amplifiers, current sources or transistor arrays.

In modern semiconductor technology , the preparation costs for the production of gate arrays are relatively high, while the actual production costs are low. Gate arrays are interesting for small series production and can contain several million logic circuits. They are therefore seen as a very highly standardized form of ASIC and are classified between partially customer-specific circuits made from standard circuit cells and logic circuits (PLDs) or programmable logic arrangements (PALs) that can be programmed by the user or customer .

Gate arrays are not to be confused with Field Programmable Gate Arrays (FPGA), which have meanwhile taken a large part of the market for application-specific integrated circuits (IC) from the “gate array” technology. They also use a programmable matrix arrangement, but in contrast to gate arrays, this is done by the user. Their manufacturing approach is therefore different and they are to be classified in competition with complex programmable logic circuits such as Generic Array Logic (GAL) and above all Complex Programmable Logic Device (CPLD).

A via mask programming produced semiconductor read-only memory (Engl. Read-only memory , ROM) uses the same manufacturing approach to memory circuits.

Manufacturing

The manufacture of a gate array circuit took place, among other things, in the form of a typical CMOS process from the 1970s or 1980s, that is to say usually in an aluminum or polysilicon gate technology with a gate length of 1 µm or 3 µm and a maximum of 2 aluminum wiring levels. The majority of the manufacturing process is carried out by the manufacturer completely independently of a subsequent customer. This includes the entire front-end of line , i.e. the production of all transistors, resistors, capacitors and diodes as well as the first insulation layer and all contact holes over the entire structure. Then the wafers with the “unfinished” circuits can be stored until a corresponding customer order is processed.

The customer-specific part includes the application of a continuous aluminum layer (aluminum wiring technology), subsequent photolithographic structuring and etching of the metal layer to produce the conductor tracks. The photo mask required for this depends on the product and is manufactured upon customer request. The resulting conductor tracks are laid in such a way that only the basic cells or components required for the desired circuit are connected and connected via the corresponding contact holes. In the simplest form of gate array technology, this customer-specific part comprises only one wiring level, therefore only one photolithographically structured level. With improved production techniques, however, more complex wiring with two or more wiring levels and the via level in between were possible as early as the early 1980s, but they were significantly more expensive. As a result, “sea-of-gates” circuits with a higher transistor density became possible. This is followed by the isolation, bonding and housing of the circuit.

meaning

Gate array switching circuits made up the largest share for customer-specific integrated circuits (ASICs) with a market share of over 40% in the late 1980s and early 1990s. In the following years the importance of the gate array switching circuits decreased continuously and in 1998 only accounted for approx. 20% of the ASIC market.

Structure of a ULA

The ULA ( uncommitted logic array or universal logic array ) contains a grid structure of several inputs and their negations. The AND gates included are already permanently connected by the manufacturer to at least two inputs or their negations (mask-programmed). However, every AND gate has an input that has not yet been assigned. During programming, the user can chain this input either to a logical zero (ground) or a logical one (operating voltage) internally in the IC. The AND gates connected to ground are therefore inactive, those connected to operating voltage (H) are activated. The OR gate following at the outputs of the AND gates is already firmly chained / connected by the manufacturer (mask programmed). The AND gates that have been switched to active are referred to in their entirety as the set of settings , those that are inactive as the set of zeros .

With the ULA, only the internal AND elements can be switched to active or passive. Their logical assignment to the inputs is already given. The OR element cannot be influenced in the ULA. The output of the OR gate is the output of the ULA.

Alternative names and similar technologies

There are many different approaches in the custom circuit market. Offers range from partially or completely customer-specific integrated circuits (design at the customer; no longer changeable after production) to flexible logic circuits that can be programmed by the user and also re-programmable. The gate arrays linked by the manufacturer according to customer specifications represent a middle ground here. It uses a flexible arrangement for the production of a wide variety of logic circuits, but cannot be changed by the customer or subsequently. Sea-of-gate circuits are a sub-class or further development of gate arrays .

Alternative names to gate arrays are:

  • uncommitted logic array (ULA, roughly "unwritten logic array"): originally a trademark of Ferranti Pic., UK. This is an unwritten / unbound master-slice arrangement with component-level cells.
  • uncommitted component array (UCA): Another / more precise term for ULA
  • uncommitted gate array (UGA): A master slice arrangement with cells at the functional level.

There are also other programmable logic circuits based on matrices of logic gates. However, other logic gates are used and programming is carried out by the customer himself. These include:

Gate array manufacturer

literature

  • Peter Ammon: Gate arrays, application-specific integrated circuits. Hüthig Buch Verlag, Heidelberg 1985, ISBN 3-7785-1063-0 .
  • Design and simulation of gate arrays with personal computers. In: Design & Electronics. 18, 1986.
  • HCMOS Gate Array Design Manual. Texas Instruments Germany GmbH
  • Andy Rappaport: Experience with gate arrays. Te-Wi-Verlag, Munich 1985, ISBN 3-921803-47-0 .
  • The Programmable Gate Array Design Handbook. 1st edition, Xilinx, 1986.
  • Trevor York: Gate array architectures . In: Microprocessors and Microsystems . tape 12 , no. 6 , July 1, 1988, pp. 323-330 , doi : 10.1016 / 0141-9331 (88) 90189-5 .
  • Manfred Seifart, Helmut Beikirch: Digital circuits. 5th edition. Verlag Technik, Berlin 1998, ISBN 3-341-01198-6 .
  • Monolithic Memories announces: a revolution in logic design. In: Electronic Design. 26, No. 6, Hayden Publishing, Rochelle, NJ, March 18, 1978, pp. 148B-148C.
  • Hans Martin Lipp: Basics of digital technology . Oldenburg Wissenschaftsverlag, ISBN 978-3-486-25916-2 (ULA on p. 169–170; PLA on p. 172).

Web links

Individual evidence

  1. ↑ Chapter 9 Lexicon of the ASIC. In: A. Auer: Programmable logic IC, properties, application, programming. Hüthig Buch Verlag, Heidelberg 1990, p. 191.
  2. ^ Ming-Bo Lin: Introduction to VLSI Systems: A Logic, Circuit, and System Perspective . CRC Press, 2011, ISBN 978-1-4398-6859-1 , pp. 654 .
  3. ^ Eugene D. Fabricius: Modern Digital Design and Switching Theory . CRC Press, 2017, ISBN 978-1-351-43054-8 , Chapter 9: Application-Specific Integrated Circuits .
  4. ^ A b Stanley L. Hurst: Custom-Specific Integrated Circuits: Design and Fabrication . CRC Press, 1985, ISBN 978-0-8247-7302-1 , pp. xvii & 22 .
  5. ^ Manfred Seifart : Digital circuits. 2nd edition VEB Verlag Technik Berlin, Berlin 1986, ISBN 3-341-00148-4 , chap. Semi-customer circuits, gate arrays , pp. 29–31.
  6. ↑ Christian Ellwein: Programmable logic with GAL and CPLD: Introduction to circuit development with logic modules in ISP technology . Oldenbourg Industrieverlag, 1999, ISBN 978-3-486-24610-0 , p. 1 .
  7. ^ A b Trevor York: Gate array architectures . In: Microprocessors and Microsystems . tape 12 , no. 6 , July 1, 1988, pp. 323-330 , doi : 10.1016 / 0141-9331 (88) 90189-5 .
  8. ↑ a b c d e f g h i j C. S. Choy, CH Fung, CF Chan: Selection assistant system for gate array user . In: Engineering Applications of Artificial Intelligence . tape 6 , no. 6 , December 1, 1993, pp. 519-531 , doi : 10.1016 / 0952-1976 (93) 90049-4 .
  9. ^ John G. Webster (Ed.): Wiley encyclopedia of electrical and electronics engineering . John Wiley, New York 1999, ISBN 0-471-13946-7 , pp. 545-546 .
  10. ↑ Hans Martin Lipp: Fundamentals of digital technology. Oldenburg Wissenschaftsverlag, ISBN 978-3-486-25916-2 , ULA , p. 169 (ULA "Universal Logic Array", limited preview in the Google book search).
  11. ↑ Hans Martin Lipp: Fundamentals of digital technology. Oldenburg Wissenschaftsverlag, ISBN 978-3-486-25916-2 , pp. 169–170 (logical structure of the ULA "Universal Logic Array", limited preview in the Google book search).
  12. ↑ H.Krug: Changeable gate arrangements (AGA). In: Design & Electronics. No. 18, 1986.