Programmable logic circuit

A programmable logic circuit , often referred to in German-language specialist literature as a programmable logic device or PLD for short , is an electronic component for integrated circuits . Unlike logic gates , which have a fixed function, PLDs only receive their function after production through the corresponding programming (configuration). PLD is the generic term for logic IC technologies such as PAL , PLA , GAL , CPLD and for newer technologies such as FPGAs .

Differentiation according to complexity

Examples of differently complex PLDs are (in increasing complexity):

Basic principle of a PLA

Simple programmable logic circuits usually consist of an array of AND operations followed by an array of OR operations .

• Programmable Read-Only Memory (PROM)
  A PROM represents a fixed AND array with a programmable OR array or a lookup table (LUT).
• Programmable Array Logic (PAL) or Generic Array Logic (GAL)
  A PAL represents a programmable AND array with a fixed OR array. In contrast to a PAL, a GAL is rewritable.
• Programmable Logic Arrangement (PLA)
  In a PLA, both the AND array and the OR array are programmable.

PLAs were mostly used to replace so-called glue logic . They are now rarely used and have been replaced by the following PLDs.

• Complex Programmable Logic Device (CPLD)
  A CPLD consists of blocks that contain a PLA, input and output blocks, and programmable feedback. These blocks can be interconnected. A flip-flop is usually included for each I / O pin .
• Field Programmable Gate Array (FPGA)
  Similar to a CPLD, an FPGA consists of interconnected blocks, but these are more complex. A block here consists of flip-flops and LUTs. The options for interconnecting these blocks are also greatly expanded compared to the CPLD. An FPGA often also contains ready-made function blocks such as RAM, PLLs or entire CPU cores.

CPLDs such as FPGAs also often offer programmable I / O cells that allow various signal interfaces (e.g. TTL , PCI or LVDS ) to be connected to the component. See also: Differences between CPLDs and FPGAs

Differentiation according to programmability

• Mask-programmed
  Here the configuration is already defined during the production of the component (see gate array ). If FPGAs are to be used in large numbers, they can be ordered mask-programmed from some manufacturers. This saves additional production steps and the external components required for configuration.
• One Time Programmable (OTP)
  Here there is programming by burning connections (fusible link) or creating connections with the antifuse technology.
• Erasable Programmable Read Only Memory (EPROM)
  EPROM programming was mostly only used for PLAs.
• Electrically Erasable Programmable Read-Only Memory (EEPROM) or Flash
  GALs are EEPROM programmed and can therefore, unlike PALs, be reused. The configuration of CPLDs usually takes place via flash memory. Programming via EEPROM or Flash has the advantage that the component is ready configured immediately after switching on.
• SRAM based
  The configuration of FPGAs is usually SRAM based. This must first be loaded into the component after switching on the FPGA, either by a configuration PROM or a connected microprocessor . An FPGA can even be completely or partially reprogrammed during operation, e.g. B. to change a running processing algorithm. One area of ​​application for this is reconfigurable computing .

See also

• Configurable Logic Block

literature

• A. Auer: PLD manual, tables and data, microelectronics 6. Hüthig-Verlag, Heidelberg 1990, ISBN 978-3-7785-1991-2 .
• Erwin Böhmer, Dietmar Ehrhardt, Wolfgang Oberschelp: Elements of applied electronics. 15th edition. Vieweg Verlag, Wiesbaden 2007, chapter ROMs, PROMs and PLDs. (ROM, PLD and PAL on p. 268–269, structure and programming of GALs in the appendix p. 418–419, structure of the various PLD technologies p. 418).

Web links

Commons : Programmable logic circuit  - collection of images, videos and audio files

Individual evidence

1. ↑ Erwin Böhmer, Dietmar Ehrhardt, Wolfgang Oberschelp: Elements of applied electronics. 15th edition. Vieweg Verlag, Wiesbaden 2007, structure of the PLDs p. 418 (chapter “ROM, PLD and PAL” on p. 268–269, structure and programming of GALs in the appendix p. 418–419).