Low voltage differential signaling
The English term Low Voltage Differential Signaling (LVDS) is an interface standard for high-speed data transmission . LVDS is standardized according to ANSI / TIA / EIA -644-1995. It describes the physical layer , not the higher protocol layers on top of it .
Important physical characteristics are:
- differential voltage levels
- relatively low voltage level (English low voltage )
- the signals are generated with a constant current source
Applications
Its main applications are in high-speed serial transmissions at a few Gbit / s. Typical applications of LVDS are Serial ATA (SATA), PCI Express (PCIe), FireWire , HyperTransport , video interfaces such as DisplayPort and also field buses such as SpaceWire and RapidIO . Furthermore, mostly proprietary digital interfaces of liquid crystal display modules in embedded application areas and in laptops , where the display is permanently integrated into the housing, are based on LVDS.
Digital video interfaces between PC and an external monitor, such as Digital Visual Interface (DVI) or HDMI , on the other hand, are physically based on Transition-Minimized Differential Signaling (TMDS), which is basically similar but optimized for longer transmission distances .
Voltage level
Low voltage (low voltage ) means that instead of a conventional high (high voltage) voltage for digital systems of 5 V or 3.3 V, a lower voltage is used. This has several advantages. With classic interfaces such as EIA-422 , a relatively high power is required to change the charge on the cable. The voltage changes occurring (high d U / d t ) and high-frequency charging and discharging (high d i / d t ) are associated with high-frequency electric (E) field and (H-field) magnetic fields which strong electromagnetic interference represent . The high-frequency recharging currents also cause problems on the power supply lines. The ever further shrinking of the structure of modern semiconductors also leads to a reduction in the supply voltages. At high data rates, there is therefore no way around reducing the signal level. LVDS works with a voltage swing of 350 mV. Differential signal transmission means that two lines are used and the difference in the voltages is decisive for the logic state. With LVDS, the difference is 350 mV, while the absolute voltage to ground is around 1200 mV. A logic change is generated by opposing changes in the voltage on both lines. This is known as symmetrical signal transmission . One line is always on the high level and the other line on the low level, so both change when the signal level changes.
| V ee | V OL | V OH | V cc | V CMO |
| GND | 1.0V | 1.4V | 2.5-3.3V | 1.2V |
Working principle
On the driver side a generated constant current source a current of 3.5 mA. This is switched between the two signal lines depending on the logic level of the input signal. The other line is connected to the zero level. On the receiver side, the current flows through a terminating resistor of 100 Ω. This value corresponds to the wave resistance of the line. This largely avoids a reflection back to the signal source. The signal current generates a voltage change in the receiver from +350 mV to −350 mV and vice versa.
Layout (track routing)
The low voltage levels make LVDS signals sensitive to electromagnetic interference. A suitable layout can counteract susceptibility to interference.
It is advisable to run the outgoing and return conductors close together, or to design a conductor over a ground plane in such a way that the line impedance is set by the geometry and the dielectric of the circuit board. Due to the small area that the closely spaced conductors span, even a small magnetic flux of an electromagnetic field can impress a voltage difference as a push-pull interference on the line. With LVDS transmission, the receivers are tolerant of common-mode interference up to 1000 mV.
The closely spaced lines also cause only a small amount of radiation of the push-pull useful signal. Nevertheless, if a circuit is inexpediently implemented, undesired common-mode signals can also arise along a well-routed line arrangement, which lead to the undesired emission of an electromagnetic wave . However, these can be influenced by an overall EMC- compatible design of the circuit and not just by the wiring.
In the case of transmission links in the Gbit / s range, runtime differences between the paths and possibly also to other LVDS channels must be avoided. The same conductor lengths are therefore required for synchronous signal transmission. This condition can be achieved with meandering conductors.
LVDS is z. B. for input and output channels integrated in FPGAs . Manufacturers such as Xilinx specify the cable lengths within the housing as what is known as "flight time". The name suggests a time, but it is the cable length in millimeters.
Data rates
The maximum data rate of an LVDS interface depends on the cable quality. With Cat-5 cable UTP , a cable length of around 2 m is typically possible at a data rate of 200 Mbit / s. According to the current state of the art, the limit is several GBit / s.
See also
Individual evidence
- ↑ Interfacing Between LVPECL, VML, CML and LVDS Levels (PDF; 259 kB), requested on February 20, 2015, engl.