PCI Express

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PCI Express logo
PCI Express × 1 slot

PCI Express ("Peripheral Component Interconnect Express", abbreviated to PCIe or PCI-E ) is a standard for connecting peripheral devices to the chipset of a main processor . PCIe is the successor to PCI , PCI-X and AGP and offers a higher data transfer rate per pin compared to its predecessors .

In addition to being used for expansion slots, the PCIe protocols now form the basis for numerous other interfaces such as SATA Express , M.2 , U.2 , SAS Express and Thunderbolt .

During its development, the interface was called "3GIO", which stands for "3rd Generation Input / Output ".


version 1.0 / 1.1 2.0 / 2.1 3.0 / 3.1 4.0 5.0 6.0
Release 2003 2007 2010 2017 2019 2021
Walking pace 2.5  GT / s 5 GT / s 8 GT / s 16 GT / s 32 GT / s 64 GT / s
Line code 8b / 10b 128b / 130b PAM-4
Security code –– RS (544,514)
Lanes Transmission rate
(burst rate in 10 9 bytes / s without protocol overhead )
(× 10) 0.25 0.5 00.985 01,969 03,938 007.529
(× 2)0 0.50 1.0 01,969 03,938 07,877 015.059
(× 40) 1.00 2.0 03,938 07,877 15.754 030.118
(× 80) 2.00 4.0 07,877 15.754 31.508 060.235
(× 16) 4.00 8.0 15.754 31.508 63.015 120.471
PCI Express graphics card

In contrast to the parallel PCI bus, PCIe is not a shared bus system, but consists of point-to-point connections dedicated to each device . Individual components are connected via switches. These make it possible to establish direct connections between individual PCIe devices so that communication between individual devices does not affect the data rate that can be achieved by other devices.

The individual point-to-point connections of PCI-Express are carried out through one or more lanes of a self- clocked serial connection. There is no separate clock signal, only a much lower reference clock of 100 MHz is transmitted separately, which is not used for transmission. The clock is recovered from the received signal. This is specially coded for this (up to PCIe 2.1 according to 8b / 10b, PCIe 3.0 to 5.0 a “scrambling” coding, which precedes 128 net data bits with 2 synchronization bits each). As of PCIe 6.0, 2 bits are transmitted per symbol; in addition to a synchronization symbol, 15 symbols are added for forward error correction.

Parallel-to-serial converters are used in the modules for sending the data and serial-to-parallel converters for receiving. Despite this very different physical structure, PCIe is fully compatible with PCI in terms of software, so that neither operating systems, drivers nor application programs need to be adapted.

PCIe is full-duplex (dual-simplex) and works, depending on the version, with 250, 500, 985 , 1969 or 3938  MB / s per lane and direction. PCIe 6.0 with 7529  MB / s per lane and direction is in the development phase .

All data transfers and all signals (e.g. IRQs ) on the PCIe connection are divided into packets. Due to the fundamentally different electrical structure and the different form of transmission, no mixing devices are possible that could be operated in both PCI and PCIe slots. This is also due to other connections, so that newer motherboards or controllers must be used for PCIe cards.

Like PCI, PCIe is basically hot-pluggable , which enables (e.g. defective) expansion cards to be installed and removed during operation, provided the hardware and the operating system support this.


PCI-Express can be connected via three different electrical topologies:

  • PCI Express device on the system board
  • PCI Express devices connected via a connector on the system board in which an add-on card is inserted
  • PCI Express devices are connected by two connectors: one on the system board with a riser card and one or more add-on cards in the slot (s) of the riser card (used by PCI Express 4 passively no longer supported).

In addition to the standard bus widths, the latter also have × 16 (as two × 8), × 24 (as three × 8), × 32 (as two × 16) or × 48 (as three × 16).

The × 24, × 32 and × 48 slots available on the market are riser slots for accommodating expansion cards, which can then accommodate 1 to 3 PCI × 8 or × 16 cards.

Transfer layers

The transmission is represented by several layers , each of which only communicates with the directly adjacent layers and carries out error detection or correction for the data transmitted on this layer.

The lowest layer, the so-called physical layer , represents the electrical connection between two devices that are directly connected to one another. These are, for example, a terminal device (e.g. a plug-in card) and the closest switch. The logical connection ("link") between these devices consists of 1 to 16 lanes . Each lane in turn consists of two pairs of lines, one differential pair each for sending and receiving ( dual-simplex ).

All data that is transmitted between PCIe devices is mixed and transmitted over these lines, in contrast to PCI there are no longer any separate lines for signaling interrupts . However, since the serial protocol cannot be stopped, the result is a slightly higher and fluctuating interrupt latency than with classic PCI with dedicated interrupt lines.

The data link layer transfers the data packets of the transaction layer between the two connection partners. To do this, it provides this with a sequence number and a 32-bit CRC value, the so-called Link CRC (LCRC) . Received packets are communicated to the direct connection partner using data link layer packets, as is the status of the packet. Damaged or lost packets are sent again by the connection partner. This decouples the higher layers from electrical transmission interference.

The transaction layer ultimately transports the user data between the logical sender and receiver, i.e. without taking into account the switches in between. The Transaction Layer Packets (TLP) contain an identifier in the header of what type of transmission it is. Typical examples are write accesses (Writes) and read requests (Reads) and read replies (Completions). Write accesses are so-called posted transactions , that is, they are sent and do not generate any response on the transaction layer.

Quality of Service

PCIe offers " Quality of Service " as a new feature compared to PCI . For this purpose, "Virtual Channels" (VC) are used, to which a "Traffic Class" (TC) priority is assigned. By default, data traffic runs via VC0 with TC0. By using other virtual channels, certain data traffic can be prioritized.

A typical application would be a sound card during recording: If it cannot send your data on over the connection in good time because the connection is otherwise occupied, sooner or later the buffer of the sound card will overflow and data will be lost. For this real-time application , one would prioritize the data traffic.

Power supply

PCIe power connector
left: 8-pin, right: 6-pin

A PCI Express slot can supply the connected device with power. According to the specification, the power delivered for a normal slot such as PCI is a maximum of 25 watts, for low-profile cards a maximum of 10 watts and for a PEG (PCIe × 16) slot a maximum of 75 watts. Since this is often too little for some purposes such as graphics cards or USB 3.0 cards, the specification provides for different additional connectors for power supply, so-called PCI Express (Graphics) Power Supply Connector (also PEG connector or PCIe cable), the +12 Supply volts.

The first version of the additional connector has 6 pins and can deliver up to 75 watts, which increases the maximum power provided to the device to 150 watts, and when using two such plugs to 225 watts. In the specification of PCI Express 2.0, a new additional connector with 8 pins was defined, which can carry a maximum of 150 watts. For even higher performance, an additional connector with 6 pins can be used, which supplies an additional 75 watts, whereby the maximum power consumption of a PCI Express card is limited to 300 watts (75 watts from the slot, 150 watts first connector, 75 watts second connector ). New, more powerful graphics cards, which have been on the market since the beginning of 2011, provide for the use of two 8-pin connectors. This increases the maximum power consumption to 375 watts. (75 watts from the slot, 150 watts first plug, 150 watts second plug). This last extension is not yet official, but is already being used in corresponding products.

Power connector
6-pin (max. 75 W) 8-pin (max. 150 W)
Pin code PCIe6connector.png description Pin code PCIe8connector.png description
01 +12 V 01 +12 V
02 not connected (mostly +12 V) 02 +12 V
03 +12 V 03 +12 V
04th Sense1 (8-pin connected)
04th Dimensions 05 Dimensions
05 Sense (6-pin connected) 06th Sense0 (6- or 8-pin connected)
06th Dimensions 07th Dimensions
08th Dimensions

If a 6-pin plug is plugged into an 8-pin socket, the card notices from the missing Sense1 that it can only draw 75 W via the cable connection.

Slot variants

Lanes Number of plug contacts Mechanical length (mm)
Left right total Left web right total
× 1 22nd 14th 36 11.65 1.78 07.65 21.08
× 4 42 64 21.65 31.08
× 8 76 98 38.65 48.08
× 16 142 164 71.65 81.08

PCI Express cards and PCI Express slots have two parameters:

  • The mechanical length of the slot: Depending on the length of the slot or slot, one speaks of PCIe × 1, PCIe × 4, PCIe × 8 or PCIe × 16. There are also "open" slots into which cards of any length can be mechanically inserted. However, the card detection by the # PRSNT contacts no longer works there.
  • The maximum usable lanes of a slot or a PCIe card: They often correspond to the mechanical length, but can also be smaller, but never larger. Often found are mechanical × 16 slots that are only × 4 or × 8 electrical. In particular, it is often the case that boards with several × 16 slots provide fewer lanes when used at the same time (see below).

In the desktop area, × 1 is usually used as a replacement for the PCI bus and × 16 as a replacement for the AGP slot for connecting graphics cards . × 4 is mainly found in the server area for cards with high throughput (hard disk controllers, 10GE network cards ).

There are also the PCIe variants × 4 and × 8. The slots are also downward compatible, i.e. a × 1 card can also be plugged into a × 4 slot, for example; only one of the four lanes of the slot is then used. Some motherboards have PCIe slots without a connecting bar (“open” slot) so that “larger” cards can be inserted. It is even possible to saw open closed slots, but there is a risk of the saw mechanically destroying the mainboard. In addition, no mainboard components such as capacitors , pin headers or SATA connections may block the long connection on the card.

It is also possible that slots have a connection to the lanes that differs from the design. This can often be found with SLI and Crossfire, for example . Because although the slots for the graphics cards have the size of × 16 slots, when two graphics cards are used, the 16 lanes are distributed over both slots if the motherboard or the chipset used on it does not provide 32 lanes for both graphics cards, which is then only possible Eight lanes per card. However, this reduction in transmission capacity does not only take place with two graphics cards, but also, for example, when using a × 16 graphics card and a × 1 card, so that the graphics card only runs with × 8. The reduction in the lanes does not reduce the performance by the same factor: a test in 2011 by masking the contacts of some of the last PCIe 2.0 cards showed that mostly only minor performance losses were found. Down to PCIe 2.0 × 4, the loss was mostly measurable at best, while PCIe 2.0 × 1 had a negative effect especially if the memory of the graphics card was too small.

The slot is mechanically divided into two areas: In the left area there are always 22 plug-in contacts, which are mainly responsible for the power supply and the management communication ( SMBus , JTAG ). In the right-hand area there are 14 to 142 plug-in contacts, depending on the number of connections, which are designed for the actual transmission of user data and other signals.

In addition, there are miniaturized versions of PCIe in notebooks , including ExpressCard , PCI Express Mini Card and M.2 for extensions such as WLAN and SSD or as Mobile PCI Express modules for graphics cards. Initially in servers , now also in desktop computers and notebooks, SSDs are also addressed directly via PCI Express, see U.2 and NVMe .

Pin assignment

PCIe × 1, × 4, × 8 and × 16 occupancy
Pin code above below designation
1 + 12V PRSNT1 # Present 1: Is only connected to
the rearmost PRSNT2 # pin on the card
, all other PRSNT2 # pins are
not connected to anything on the card.
2 + 12V + 12V
3 + 12V + 12V
4th Dimensions Dimensions
5 SMCLK TCK SMBus and JTAG connectors
7th Dimensions TDO
8th + 3.3V TMS
9 TRST # + 3.3V
10 + 3.3V aux + 3.3V Standby operating voltage
11 WAKE # PERST # Reactivation; voltages and reference clock stable?
Coding gap (web in the slot)
12 reserved Dimensions
13 Dimensions REFCLK + Reference clock: + and -
14th HSOp (0) REFCLK−
Lane 0: transmitter, + and -
15th HSOn (0) Dimensions
16 Dimensions HSIp (0) Lane 0: receiver, + and -
17th PRSNT2 # HSIn (0)
Present 2: for × 1 cards
18th Dimensions Dimensions
continued: PCIe × 4, × 8 and × 16 allocation
Pin code above below designation
19th HSOp (1) reserved Lane 1: Sender, + and -
20th HSOn (1) Dimensions
21st Dimensions HSIp (1) Lane 1: Receiver, + and -
22nd Dimensions HSIn (1)
23 HSOp (2) Dimensions Lane 2: Sender, + and -
24 HSOn (2) Dimensions
25th Dimensions HSIp (2) Lane 2: Receiver, + and -
26th Dimensions HSIn (2)
27 HSOp (3) Dimensions Lane 3: Sender, + and -
28 HSOn (3) Dimensions
29 Dimensions HSIp (3) Lane 3: Receiver, + and -
30th reserved HSIn (3)
31 PRSNT2 # Dimensions Present 2: for × 4 cards
32 Dimensions reserved
Dimensions 0 V, reference
care Supply voltage to the PCIe card
output Signal from the card to the motherboard
entrance Signal from the motherboard to the card
open drain may be
switched to ground and / or read from several cards
Detection of the bus width
(× 1, × 4, × 8, × 16) of the card
reserved not yet in use
continued: PCIe × 8 and × 16 occupancy
Pin code above below designation
33 HSOp (4) reserved Lane 4: Sender, + and -
34 HSOn (4) Dimensions
35 Dimensions HSIp (4) Lane 4: Receiver, + and -
36 Dimensions HSIn (4)
37 HSOp (5) Dimensions Lane 5: Sender, + and -
38 HSOn (5) Dimensions
39 Dimensions HSIp (5) Lane 5: Receiver, + and -
40 Dimensions HSIn (5)
41 HSOp (6) Dimensions Lane 6: Sender, + and -
42 HSOn (6) Dimensions
43 Dimensions HSIp (6) Lane 6: Receiver, + and -
44 Dimensions HSIn (6)
45 HSOp (7) Dimensions Lane 7: Sender, + and -
46 HSOn (7) Dimensions
47 Dimensions HSIp (7) Lane 7 receivers, + and -
48 PRSNT2 # HSIn (7)
Present 2: for × 8 cards
49 Dimensions Dimensions
continued: PCIe × 16 allocation
Pin code above below designation
50 HSOp (8) reserved Lane 8: Sender, + and -
51 HSOn (8) Dimensions
52 Dimensions HSIp (8) Lane 8: Receiver, + and -
53 Dimensions HSIn (8)
• • • • • • • • •
80 Dimensions HSIp (15) Lane 15: Receiver, + and -
81 PRSNT2 # HSIn (15)
Present 2: for × 16 cards
82 reserved Dimensions

Compatibility by number of lanes

The PCIe standard requires that each card be able to connect to both a lane width and the number of lanes electrically supported by the card. The same applies to slots. Other link widths - the standard provides × 1, × 4, × 8 and × 16 - are not covered by the standard. A connection is then established with the maximum width supported by both the slot and the card.

Since the electrical width can be smaller than the structural shape and some link widths are optional, it is not obvious what width a card will work with in a given slot. The "PCI Express Label Specification and Usage Guidelines" from 2006 therefore recommend that you list exactly which connection widths are supported for each slot and card. However, this is rarely implemented.

map slot
0× 1 0× 4 0× 8 × 16
0× 1 OK OK OK OK
0× 4 ~ OK OK OK
0× 8 ~ OK OK
× 16 ~ OK
OK Compatible
~ Partly compatible: Only for slots that do not prevent the card from being physically inserted ("open slots",
without mainboard components behind them), transfer rate is limited to the maximum slot transfer rate. This is used, for
example, for slots that are similar in construction to a × 16 slot, but only have 8 lanes with electrical
connections. × 16 cards work there, but only with half the bandwidth.

Compatibility according to PCIe versions

PCIe plug-in cards and slots are generally downward compatible with counterparts of all previous generations. The transmission takes place on the basis of the fastest, common protocol. This means that, for example, a PCIe 1.0 card in a 3.0 slot only transmits at 2.5 GT / s, whereas a PCIe 2.0 card in the same slot transmits with 5 GT / s.


  • Ravi Budruk et al: PCI Express System Architecture . Addison-Wesley, Boston 2004, ISBN 0-321-15630-7
  • Franz-Josef Lintermann, Udo Schaefer, Walter Schulte-Göcking, Klaas Gettner: Simple IT systems. Textbook / specialist book . 5, 1st corrected reprint edition. Bildungsverlag EINS, 2008, ISBN 978-3-8237-1140-7 (pages 64-66).

Web links

Commons : PCI Express connectors  - collection of pictures, videos and audio files

Individual evidence

  1. PCI-SIG Releases PCIe 4.0, Version 1.0 . PCI-SIG. Retrieved October 26, 2017.
  2. a b PCI Express Base Specification Revision 5.0. Retrieved December 12, 2018 .
  3. https://www.heise.de/newsticker/meldung/PCIe-6-0-verdoppel-Datdurchsatz-erneut-4450314.html
  4. Claire Castellanos Nereus: PCI-SIG Announces PCI Express 4.0 Evolution to 16GT / S, Twice the Throughput of PCI Express 3.0 Technology. (No longer available online.) PCI-SIG, November 29, 2011, archived from the original on December 23, 2012 ; accessed on May 19, 2013 (English).
  5. PCI-SIG Announces Upcoming PCI Express 6.0 Specification to Reach 64 GT / s. June 18, 2019, accessed November 15, 2019 .
  6. Benjamin Benz: Steiniger Weg - How serial interconnects beat physics a little, c't 10/2010, pp. 188–191.
  7. Christof Windeck: What is PEG? What is the difference between PCI Express and PCI Express for Graphics (PEG)? In: c't magazine. 2009, accessed on October 12, 2010 (from c't 1/09).
  8. PCI Express Power (6 pin). In: hardwarebook.info. 2007, accessed October 12, 2010 .
  9. a b Real power consumption of current graphics cards. PCIe power supply - 6/8 pin connector. In: Hard Tecs 4U. January 29, 2009, accessed on October 12, 2010 (graphic representation of the pin assignment).
  10. The Quick PCI-Express 2.0 Guide. In: 10stripe.com. Retrieved October 12, 2010 .
  11. Product index NVidia Technical data Geforce GTX 590. 2011, accessed on May 8, 2011 .
  12. System requirements AMD Radeon 6990 graphics card. 2011, Retrieved May 8, 2011 .
  13. PCI Express x16 Graphics 150W-ATX Specification Revision 1.0
  14. PCI Express 225 W / 300 W High Power Card Electromechanical Specification Revision 1.0
  15. PCI Express Card Electromechanical Specification Revision 3.0
  16. ^ Yun Ling: PCIe Electromechanical Updates . May 16, 2008. Archived from the original on November 5, 2015. Retrieved on November 7, 2015.
  17. Andreas Link: You can force a PCI-E x16 graphics card into the x8 slot? Go! . In: PC Games Hardware . April 12, 2016. Retrieved December 16, 2018.
  18. Wolfgang Andermahr: PCIe interfaces in the test: x16, x8, x4, x1 - how much is necessary? (Pages 3-5) . In: ComputerBase . August 29, 2011. Retrieved December 16, 2018.
  19. ^ What is the A side, B side configuration of PCI cards . In: Frequently Asked Questions . Adex Electronics. 1998. Retrieved October 24, 2011.
  20. FAQ: PCI Express 4.0 - Will PCIe 4.0 products be compatible with existing PCIe 1.x, PCIe 2.x and PCIe 3.x products? . PCISIG. Retrieved February 11, 2016.