Static random-access memory
Static random-access memory (German: static RAM , abbreviation: SRAM) refers to an electronic memory module . Together with the dynamic RAM (DRAM), it forms the group of volatile (volatile; engl. Volatile ) memory, that is, the stored information is lost when switching off the operating voltage. Unlike DRAM, SRAM does not require periodic (dynamic) refresh (Engl. Refresh ) to avoid loss of data in each data cell, but retains its data information, as long as the operating voltage is present.
Properties and structure
The information is saved by changing the state of a bistable multivibrator in the form of a flip-flop per bit. Although this allows the memory cell to be read out quickly, the memory cell is relatively large in comparison to dynamic memory cells and therefore the storage capacity of the entire chip is correspondingly smaller. In static operation (holding information), the power requirement of a cell is very small.
Nowadays, SRAMs are mostly manufactured as 6-transistor cells (6T SRAM cells) using CMOS technology. The construction of a multivibrator with resistors as load elements (so-called 4T SRAM cell) is no longer used; Instead of load resistors, p-channel MOS transistors are used today. With a further two transistors for coupling to the column or row selection lines, the said 6-transistor cell results as shown in the attached picture. Because of this more complicated structure, an SRAM cell consumes significantly more chip area than a DRAM cell (over 140 F² ). In principle, every bit in the SRAM cell is stored in four transistors that form two inverters connected to one another . This memory cell has two stable states that represent 0 and 1. The two additional access transistors are used to control access to the memory cell during read and write access.
In addition to the 4T and 6T SRAM design, there are numerous alternative variants that use additional transistors to provide additional functions (e.g. separate read port) or special properties (e.g. lower leakage currents, lower power consumption when writing, higher stability) should realize. The terms 5T, 7T, 8T, 9T, 10T or 12T SRAM cell used for this are not limited to a special design, cf.
functionality
An SRAM cell has three different states. These are: Standby (waiting for access), read access (memory status was requested) and write access (memory status will be overwritten). These states work as follows:
Standby
If the word line is not switched, the access transistors separate the memory cell from the bit lines. The two counter-connected inverters (transistors M1-M4) mutually reinforce their current state (as long as the operating voltage is applied).
Read access
We assume that the memory state at Q is set to logic 1. Read access then starts with charging the two bit lines to half the operating voltage, followed by switching the word line to switch through both access transistors. As a second step, the respective values of Q and Q are then transferred to the bit lines; H. BL remains charged and BL is discharged to a logic 0 via M1 and M5 (M1 is activated because Q is set to a logic 1). BL is charged to logic 1 by M4 and M6 via the supply voltage. If the memory state had been 0 beforehand, the behavior would be the opposite. The difference between BL and BL can then be read out by a sense amplifier.
Write access
The write access begins with the value to be written being placed on the bitlines. So if we want to write a 0, BL is set to 0 and BL to 1. When writing a 1, the two values are swapped. The wordline is then switched so that the value is written to the memory cell. This works because the relatively weak transistors that make up the inverters can be overwritten by the relatively strong bitlines. A corresponding sizing of the transistors is necessary during manufacture so that overwriting works properly.
Interfaces
SRAMs are offered with different interfaces. As a discrete component, primarily for direct connection to microcontrollers , parallel asynchronous bus interfaces are used. The characteristic is that the memory is accessed without a clock signal . The access time per memory cell depends on the runtime and is in the range from 5 ns to almost 100 ns. In addition, there are synchronous SRAMs in which access occurs synchronously with a clock signal. As a rule, the throughput of synchronous SRAMs is higher than that of asynchronous SRAMs, since with synchronous interfaces it is possible to offset the addresses in relation to the data in a defined time using a pipeline . This brings speed advantages, especially with sequential memory accesses. An example of synchronous SRAMs are the so-called “ZBT-SRAMs” ( zero-bus-turnaround SRAM ), which are used in fast graphics memories . For use in combination with DDR and "Quad" memory, there are also SRAMs that transmit more data on both edges of the clock signal; sizes up to 144 Mibit (in the organization 8 Mi × 18) are achieved at a clock frequency of 1066 MHz.
Applications
SRAMs are used as high-speed memory with relatively small data capacity everywhere in applications where the data content to be fast in the access needs such as in processors as cache and on digital or mixed-signal - ICs such as FPGAs as local memory on the chip.
Around the 1980s, the microprocessors needed SRAMs as external memory because they had no integrated memory. The typical modules were 5101 (still organized as four bits, called nibble ), 6116 and 6264 .
Furthermore, SRAM is used in devices in which the data content is to be saved for up to several years without a permanent power supply. Since the power consumption in the static state (no memory accesses) is in the range of a few nA , a small backup battery (possibly also a capacitor) is sufficient to provide the necessary supply voltage, for example with CMOS-RAM for storing BIOS settings in commercially available PCs . In this area of application, the SRAM, in combination with a buffer battery, usually in the form of a lithium battery, represents a special form of NVRAM ( non-volatile random-access memory ). The battery can be integrated into the chip housing of the memory module .
literature
- Ulrich Tietze, Christoph Schenk: Semiconductor circuit technology . 12th edition. Springer, Berlin 2002, ISBN 3-540-42849-6 , Static RAMs , p. 713 ff .
- Jörg Schulze: Concepts of silicon-based MOS components . Springer, Berlin 2005, ISBN 3-540-23437-3 , pp. 66-67, 297-314 .
Individual evidence
- ↑ The International Technology Roadmap for Semiconductors 2007 - Emerging Research Devices ( Memento of the original from March 26, 2010 in the Internet Archive ) Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. , Page 7 (English, PDF; 1.1 MB)
- ↑ The International Technology Roadmap for Semiconductors 2007 - System Drivers ( Memento of the original from March 6, 2009 in the Internet Archive ) Info: The archive link was inserted automatically and has not yet been checked. Please check the original and archive link according to the instructions and then remove this notice. (English, PDF; 603 kB)
- ↑ L. Chang et al. a .: Stable SRAM cell design for the 32 nm node and beyond . In: 2005 Symposium on VLSI Technology, 2005. Digest of Technical Papers . 2005, p. 128–129 , doi : 10.1109 / .2005.1469239 ( PDF ).
- ^ Forrest Brewer: Array Structured Memories. (PDF; 2.3 MB) In: VLSI Project Design, ECE 224A - Spring 2011. Accessed April 1, 2013 (presentation slides ).
- ↑ Data sheet ( page no longer available , search in web archives ) Info: The link was automatically marked as defective. Please check the link according to the instructions and then remove this notice. a synchronous ZBT-SRAM (512 Ki × 36) (English)
- ↑ Data sheet ( Memento of the original from January 1, 2010 in the Internet Archive ) Info: The archive link was automatically inserted and not yet checked. Please check the original and archive link according to the instructions and then remove this notice. (PDF; 178 kB) of an NV-SRAM. (DS2030 with 32 Ki × 8 with integrated buffer battery) (English)
